Issuing A Stop Condition - Renesas RX100 Series User Manual

RX13T Group
24.10.3

Issuing a Stop Condition

The RIIC issues a stop condition when the ICCR2.SP bit is set to 1.
When the SP bit is set to 1, a stop condition issuance request is made and the RIIC issues a stop condition when the
ICCR2.BBSY flag is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode).
A stop condition is issued in the following sequence.
Stop condition issuance
(1) Drive the SDA0 line low (high level to low level).
(2) Ensure the low-level period of SCL0 line set in the ICBRL register.
(3) Release the SCL0 line (low level to high level).
(4) Detect a high level of the SCL0 line and ensure the time set in the ICBRH register and the stop condition setup time.
(5) Release the SDA0 line (low level to high level).
(6) Ensure the time set in the ICBRL register and the bus free time.
(7) Set the BBSY flag to 0 (to release the bus mastership).
ICBRL
SCL0
SDA0
IIC 
BBSY
MST
TRS
TDRE
STOP
SP
Figure 24.38 Stop Condition Issue Timing (SP Bit)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
ICBRH ICBRL
8
b0 ACK/NACK
Write 1 to SP bit
ICBRH ICBRL
9
Issue stop
Accept stop condition issuance
2
24. I C-bus Interface (RIICa)
Setup time Bus free time
ICBRH ICBRL
P
condition
Set STOP flag to 0
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