Renesas RX100 Series User Manual page 728

RX13T Group
CLO Bit (Extra SCL Clock Cycle Output)
This bit is used to output an extra SCL clock cycle for debugging or error processing.
Normally, set the bit to 0. Setting the bit to 1 in a normal communication state causes a communication error.
For details on this function, refer to section 24.11.2, Extra SCL Clock Cycle Output Function .
2
IICRST Bit (I C-bus Interface Internal Reset)
This bit is used to reset the internal states of the RIIC.
Setting this bit to 1 initiates an RIIC reset or internal reset.
Whether an RIIC reset or internal reset is initiated is determined according to the combination with the ICE bit. Table
24.3 lists the resets of the RIIC.
The RIIC reset initializes all registers and internal states of the RIIC, and the internal reset initializes the bit counter
(ICMR1.BC[2:0] bits), the I
the internal states of the RIIC. For the reset conditions for each register, refer to section 24.14, Initialization of
Registers and Functions When a Reset is Issued or a Condition is Detected .
An internal reset initiated with the IICRST bit set to 1 during operation (with the ICE bit set to 1) resets the internal states
of the RIIC without initializing the port settings and the control and setting registers of the RIIC when the bus or RIIC
hangs up due to a communication error.
If the RIIC hangs up in a low level output state, resetting the internal states cancels the low level output state and releases
the bus with the SCL0 pin and SDA0 pin at a high impedance.
Note: If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the
master device in slave mode, the states may become different between the slave device and the master device
(due to the difference in the bit counter information). For this reason, do not initiate an internal reset in slave
mode, but initiate restoration processing from the master device. If an internal reset is necessary because the
RIIC hangs up with the SCL0 line in a low level output state in slave mode, initiate an internal reset and then
issue a restart condition from the master device or resume communication from the start condition issuance after
issuing a stop condition. If communication is restarted by initiating a reset solely in the slave device without
issuing a start condition or restart condition from the master device, synchronization will be lost because the
master and slave devices operate asynchronously.
Table 24.3 RIIC Resets
IICRST ICE State
1 0 RIIC reset
1 Internal reset
2
ICE Bit (I C-bus Interface Enable)
This bit selects the active or inactive state of the SCL0 and SDA0 pins. It can also be combined with the IICRST bit to
initiate two types of resets. See Table 24.3 , RIIC Resets, for the types of resets.
Set the ICE bit to 1 when using the RIIC. The SCL0 and SDA0 pins are placed in the active state when the ICE bit is set
to 1.
Set the ICE bit to 0 when the RIIC is not to be used. The SCL0 and SDA0 pins are placed in the inactive state when the
ICE bit is set to 0. Do not assign the SCL0 or SDA0 pin to the RIIC when setting up the multi-function pin controller
(MPC). Note that the slave address comparison operation is carried out if the pins are assigned to the RIIC.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
C-bus shift register (ICDRS), and the I
Specifications
Resets all registers and internal states of the RIIC.
Resets the ICMR1.BC[2:0] bits, registers ICSR1, ICSR2, and ICDRS, and the internal
states of the RIIC.
24. I
2
C-bus status registers (ICSR1 and ICSR2) as well as
2
C-bus Interface (RIICa)
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