Register Descriptions; Bus Error Status Clear Register (Berclr); Bus Error Monitoring Enable Register (Beren) - Renesas RX100 Series User Manual

RX13T Group
15.3

Register Descriptions

15.3.1

Bus Error Status Clear Register (BERCLR)

Address(es): 0008 1300h
b7 b6
— —
0 0
Value after reset:
Bit Symbol
b0 STSCLR
b7 to b1 —
Note 1. Only writing 1 is effective; i.e. writing 0 has no effect.
STSCLR Bit (Status Clear)
Writing 1 to this bit clears the bus error status registers 1 and 2 (BERSR1 and BERSR2).
Writing 0 has no effect. It is read as 0.
15.3.2

Bus Error Monitoring Enable Register (BEREN)

Address(es): 0008 1304h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 IGAEN Illegal Address Access Detection
Enable
b1 TOEN Timeout Detection Enable*
b7 to b2 — Reserved
Note 1. When detection is disabled (the TOEN bit is cleared to 0), bus access can cause the bus to freeze.
Note 2. Do not set the TOEN bit to 0 (bus timeout detection disabled) while timeout errors are being detected.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Bit Name
Status Clear
Reserved
b5 b4 b3 b2
— — — —
0 0 0 0
1, 2
*
b1 b0
STSCL
—
R
0 0
Description
0: Invalid
1: Bus error status register cleared
These bits are read as 0. The write value should be 0.
b1 b0
TOEN IGAEN
0 0
Description
0: Illegal address access detection is disabled.
1: Illegal address access detection is enabled.
0: Bus timeout detection is disabled.
1: Bus timeout detection is enabled.
These bits are read as 0. The write value should be 0.
15. Buses
R/W
1
(W)*
R/W
R/W
R/W
R/W
R/W
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