24.11 Bus Hanging; Timeout Function - Renesas RX100 Series User Manual

RX13T Group

24.11 Bus Hanging

If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I
might hang with a fixed level on the SCL0 line and/or SDA0 line.
As measures against the bus hanging, the RIIC has a timeout function to detect hanging by monitoring the SCL0 line, a
function for the output of an extra SCL clock cycle to release the bus from a hung state due to clock signals being out of
synchronization, the RIIC reset function, and internal reset function.
By checking bits SCLO, SDAO, SCLI, and SDAI in the ICCR1 register, it is possible to see whether the RIIC or its
partner in communications is placing the low level on the SCL0 or SDA0 lines.
24.11.1

Timeout Function

The RIIC includes a timeout function for detecting when the SCL0 line has been stuck longer than the predetermined
time. The RIIC can detect an abnormal bus state by monitoring that the SCL0 line is stuck low or high for a
predetermined time.
The timeout function monitors the SCL0 line state and counts the low-level period or high-level period using the internal
counter. The timeout function resets the internal counter each time the SCL0 line changes (rising or falling), but
continues to count unless the SCL0 line changes. If the internal counter overflows due to no SCL0 line change, the RIIC
can detect the timeout and report the bus hung state.
This timeout function is enabled when the ICFER.TMOE bit is 1. It detects a hung state that the SCL0 line is stuck low
or high during the following conditions:
 The bus is busy (ICCR2.BBSY flag is 1) in master mode (ICCR2.MST bit is 1).
 The RIIC's own slave address is detected (ICSR1 register is not 00h) and the bus is busy (ICCR2.BBSY flag is 1) in
slave mode (ICCR2.MST bit is 0).
 The bus is free (ICCR2.BBSY flag is 0) while generation of a start condition is requested (ICCR2.ST bit is 1).
The internal counter of the timeout function works using the internal reference clock (IICφ) set by the ICMR1.CKS[2:0]
bits as a count source. It functions as a 16-bit counter when long mode is selected (ICMR2.TMOS bit is 0) or a 14-bit
counter when short mode is selected (TMOS bit is 1).
The SCL0 line level (low/high or both levels) during which this counter is activated can be selected by the setting of bits
TMOH and TMOL in the ICMR2 register. If both bits TMOL and TMOH are set to 0, the internal counter does not work.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
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24. I C-bus Interface (RIICa)
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C-bus
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