Reset From Voltage Monitor 0 - Renesas RX100 Series User Manual

RX13T Group
8.4

Reset from Voltage Monitor 0

When using the reset from voltage monitor 0, clear the voltage detection 0 circuit start bit (OFS1.LVDAS) to 0 (enabling
the voltage monitor 0 reset after a reset).
Figure 8.4 shows an example of operations for a voltage monitoring 0 reset.
Vdet0*
VPOR*
External voltage VCC
VCC
RES# pin
0
VCC
POR detection signal
(Low is valid)
0
VCC
LVD0 enable/disable
signal (Low is valid)
0
VCC
Voltage detection 0
signal (Low is valid)
0
VCC
Internal reset signal
0
VCC
RSTSR0.PORF
0
VCC
RSTSR0.LVD0RF
0
Note: For details on the electrical characteristics, see the Electrical Characteristics section.
Note 1. Vdet0 indicates the detection level for a voltage monitoring 0 reset and VPOR indicates the detection level for a
power-on reset.
Note 2. tPOR indicates the period of a power-on reset and tLVD0 indicates the period of a voltage monitoring 0 reset.
Note 3. At the time the power-supply voltage rises, VCC must rise to at least the minimum guaranteed voltage before release
from the POR reset state.
Figure 8.4 Example of Voltage Monitoring 0 Reset Operation
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
*
1
1
Power-on reset state
tPOR*
3
Voltage monitoring 0 reset state
Set by OFS1.LVDAS
2
8. Voltage Detection Circuit (LVDAb)
2
tLVD0*
RES# pin reset
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