Timer Mode Register 1 (Tmdr1) - Renesas RX100 Series User Manual

RX13T Group
19.2.3

Timer Mode Register 1 (TMDR1)

 MTU0.TMDR1
Address(es): MTU0.TMDR1 0009 5301h
b7 b6
— BFE
0 0
Value after reset:
 MTU1.TMDR1, MTU2.TMDR1
Address(es): MTU1.TMDR1 0009 5381h, MTU2.TMDR1 0009 5401h
b7 b6
— —
Value after reset: 0 0
 MTU3.TMDR1, MTU4.TMDR1
Address(es): MTU3.TMDR1 0009 5202h, MTU4.TMDR1 0009 5203h
b7 b6
— —
0 0
Value after reset:
Bit Symbol
b3 to b0 MD[3:0]
b4 BFA
b5 BFB
b6 BFE
b7 —
The TMDR1 register specifies the operating mode of each channel. The MTU has a total of five TMDR1 registers, one
each for MTU0 to MTU4. TMDR1 register values should be specified only while TCNT operation is stopped.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
BFB BFA MD[3:0]
0 0 0 0
b5 b4 b3 b2
— — MD[3:0]
0 0 0 0
b5 b4 b3 b2
BFB BFA MD[3:0]
0 0 0 0
Bit Name Description
Mode Select These bits specify the timer operating mode. Refer to Table 19.11 for
details.
Buffer Operation A 0: TGRA and TGRC operate normally
1: TGRA and TGRC used together for buffer operation
Buffer Operation B 0: TGRB and TGRD operate normally
1: TGRB and TGRD used together for buffer operation
Buffer Operation E 0: MTU0.TGRE and MTU0.TGRF operate normally
1: MTU0.TGRE and MTU0.TGRF used together for buffer operation
Reserved This bit is read as 0. The write value should be 0.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
b1 b0
0 0
b1 b0
0 0
R/W
R/W
R/W
R/W
R/W
R/W
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