Renesas RX100 Series User Manual page 709

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(2) Break Field Low Width Determination Mode

This mode is for determining the Break Field low width in the input signal on the RXDX12 pin at the reception of a Start

Frame. Setting the TMR.TOMS[1:0] bits to 01b switches operation to Break Field low width determination mode. The

TMR.TCSS[2:0] bits select the clock source for the counter. When the TCR.TCST bit is set to 1, the interface enters the

Break Field low width determinable state. Determination starts when a low level is input from the RXDX12 pin. When a

high level is then input on the RXDX12 pin, registers TPRE and TCNT are reloaded and the interface enters the Break

Field low width determinable state. When the timer underflows during Break Field low width determination, the

STR.BFDF flag is set to 1. An SCIX0 interrupt is also generated if the value of the ICR.BFDIE bit is 1. If an underflow

of the timer during data transfer cause a problem in the form of interrupt generation, stop the timer after Break Field low

width determination. Figure 23.73 shows an example of operations in Break Field low width output mode.

RXDX12 pin output

Figure 23.73

Example of Operations in Break Field Low Width Determination Mode

(3) Timer Mode

This mode is for counting cycles of the internal clock as the clock source. Setting the TMR.TOMS[1:0] bits to 00b

switches operation to timer mode. The TMR.TCSS[2:0] bits select the clock source for the counter. Counting starts when

1 is written to the TCR.TCST bit and stops when 0 is written to the TCST bit. Registers TPRE and TCNT both count

down. The TPRE register counts cycles of the clock source for counting, and underflows of the TPRE register provide

the clock source for counting by the TCNT register. When the timer underflows, the STR.BFDF flag is set to 1. An

SCIX0 interrupt is also generated if the value of the ICR.BFDIE bit is 1.

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

n = Contents of (upper) TCNT and (lower) TPRE

Determinable

Determination

Set to 1 by a program

The above diagram assumes the following:

ESMER: ESME = 1

TOMS[1:0] = 01b

23. Serial Communications Interface (SCIg, SCIh)

Determination

Determinable

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