Renesas RX100 Series User Manual page 13

14.4.4 Determining Priority ................................................................................................................. 227
14.4.5 Multiple Interrupts .................................................................................................................... 227
14.4.6 Fast Interrupt ............................................................................................................................. 227
14.4.7 Digital Filter ............................................................................................................................. 228
14.4.8 External Pin Interrupts .............................................................................................................. 228
14.5 Non-maskable Interrupt Operation .................................................................................................... 229
14.6 Return from Power-Down States ....................................................................................................... 230
14.6.1 Return from Sleep Mode or Deep Sleep Mode ........................................................................ 230
14.6.2 Return from Software Standby Mode ....................................................................................... 230
14.7 Usage Note ........................................................................................................................................ 231
14.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt ............................................... 231
15. Buses ........................................................................................................................................... 232
15.1 Overview ........................................................................................................................................... 232
15.2 Description of Buses .......................................................................................................................... 234
15.2.1 CPU Buses ................................................................................................................................ 234
15.2.2 Memory Buses .......................................................................................................................... 234
15.2.3 Internal Main Buses .................................................................................................................. 234
15.2.4 Internal Peripheral Buses .......................................................................................................... 235
15.2.5 Write Buffer Function (Internal Peripheral Bus) ...................................................................... 236
15.2.6 Parallel Operation ..................................................................................................................... 237
15.2.7 Restrictions ............................................................................................................................... 237
15.3 Register Descriptions ......................................................................................................................... 238
15.3.1 Bus Error Status Clear Register (BERCLR) ............................................................................. 238
15.3.2 Bus Error Monitoring Enable Register (BEREN) .................................................................... 238
15.3.3 Bus Error Status Register 1 (BERSR1) .................................................................................... 239
15.3.4 Bus Error Status Register 2 (BERSR2) .................................................................................... 239
15.3.5 Bus Priority Control Register (BUSPRI) .................................................................................. 240
15.4 Bus Error Monitoring Section ........................................................................................................... 242
15.4.1 Type of Bus Error ..................................................................................................................... 242
15.4.1.1
15.4.1.2
15.4.2 Operations When a Bus Error Occurs ...................................................................................... 242
15.4.3 Conditions Leading to Bus Errors ............................................................................................ 243
15.5 Interrupt ............................................................................................................................................. 244
15.5.1 Interrupt Source ........................................................................................................................ 244
16. Data Transfer Controller (DTCb) .................................................................................................. 245
16.1 Overview ........................................................................................................................................... 245
16.2 Register Descriptions ......................................................................................................................... 247
16.2.1 DTC Mode Register A (MRA) ................................................................................................. 247
16.2.2 DTC Mode Register B (MRB) ................................................................................................. 249
16.2.3 DTC Mode Register C (MRC) ................................................................................................. 251
Illegal Address Access .................................................................................................... 242
Timeout ............................................................................................................................ 242