Timer Interrupt Skipping Set Register 2 (Titcr2A) - Renesas RX100 Series User Manual

RX13T Group
19.2.40

Timer Interrupt Skipping Set Register 2 (TITCR2A)

Address(es): MTU.TITCR2A 0009 523Bh
b7 b6
— —
Value after reset: 0 0
Bit Symbol
b2 to b0 TRG4COR[2:0]
b7 to b3 —
TITCR2A specifies the interrupt skipping count for TRG4AN and TRG4BN. This setting is valid only while TITMRA is
set to 1.
Table 19.44 Setting of Interrupt Skipping Count by TRG4COR[2:0] Bits
Bit 2 Bit 1
TRG4COR[2] TRG4COR[1] TRG4COR[0]
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — TRG4COR[2:0]
0 0 0 0
Bit Name
TRG4AN/TRG4BN Interrupt
Skipping Count Setting
Reserved
Bit 0
Description
0 Does not skip TRG4AN and TRG4BN interrupts.
1 Sets the TRG4AN and TRG4BN interrupt skipping count to 1.
0 Sets the TRG4AN and TRG4BN interrupt skipping count to 2.
1 Sets the TRG4AN and TRG4BN interrupt skipping count to 3.
0 Sets the TRG4AN and TRG4BN interrupt skipping count to 4.
1 Sets the TRG4AN and TRG4BN interrupt skipping count to 5.
0 Sets the TRG4AN and TRG4BN interrupt skipping count to 6.
1 Sets the TRG4AN and TRG4BN interrupt skipping count to 7.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
Description
These bits specify the TRG4AN/TRG4BN interrupt skipping
count within the range from 0 to 7.
For details, refer to Table 19.44.
These bits are read as 0. The write value should be 0.
R/W
R/W
R/W
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