Renesas RX100 Series User Manual page 334

RX13T Group
Table 19.11 Operating Mode Setting by MD[3:0] Bits (MTU0 to MTU4)
Bit 3 Bit 2 Bit 1
MD[3] MD[2] MD[1]
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
x: Don't care
Note: Only set the corresponding operating mode listed above for each channel.
Note 1. Reset-synchronized PWM mode and complementary PWM mode can only be set for MTU3.
When MTU3 is set to reset-synchronized PWM mode or complementary PWM mode, the MTU4 settings become ineffective and
automatically conform to the MTU3 setting, respectively. MTU4 should be set to the initial values (normal mode).
BFA Bit (Buffer Operation A)
This bit specifies whether to operate TGRA in the normal way or to use TGRA and TGRC together for buffer operation.
When TGRC is used as a buffer register, TGRC input capture/output compare does not take place in modes other than
complementary PWM mode, but compare match with TGRC occurs in complementary PWM mode.
If a compare match occurs on MTU4 in the Tb interval in complementary PWM mode, the TGIEC bit in timer interrupt
enable register (MTU4.TIER) should be set to 0.
In reset-synchronized PWM mode or complementary PWM mode, buffer operation in MTU3 and MTU4 depends on the
settings in the BFA bit of MTU3.TMDR1. The BFA bit of MTU4.TMDR1 should be set to 0.
In MTU1 and MTU2, which have no TGRC, this bit is reserved. It is read as 0. The write value should be 0.
Refer to Figure 19.47 for an illustration of the Tb interval in complementary PWM mode.
BFB Bit (Buffer Operation B)
This bit specifies whether to operate TGRB in the normal way or to use TGRB and TGRD together for buffer operation.
When TGRD is used as a buffer register, TGRD input capture/output compare does not take place in modes other than
complementary PWM mode, but compare match with TGRD occurs in complementary PWM mode.
If a compare match occurs on MTU4 in the Tb interval in complementary PWM mode, the TGIED bit in timer interrupt
enable register (MTU4.TIER) should be set to 0.
In reset-synchronized PWM mode or complementary PWM mode, buffer operation in MTU3 and MTU4 depends on the
settings in the BFB bit of MTU3.TMDR1. The BFB bit of MTU4.TMDR1 should be set to 0.
In MTU1 and MTU2, which have no TGRD, this bit is reserved. It is read as 0. The write value should be 0.
Refer to Figure 19.47 for an illustration of the Tb interval in complementary PWM mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Bit 0
MD[0] Description
0 Normal mode
1 Setting prohibited
0 PWM mode 1
1 PWM mode 2
0 Phase counting mode 1
1 Phase counting mode 2
0 Phase counting mode 3
1 Phase counting mode 4
0 Reset-synchronized PWM mode*
1 Phase counting mode 5
x Setting prohibited
0 Setting prohibited
1 Complementary PWM mode 1 (transfer at crest)*
0 Complementary PWM mode 2 (transfer at trough)*
1 Complementary PWM mode 3 (transfer at crest and
trough)* 1
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
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