Receive Data Sampling Timing And Reception Margin In Asynchronous Mode - Renesas RX100 Series User Manual

RX13T Group
23.3.2

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times *
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Since receive data is sampled at the rising edge of the 8th pulse *
bit, as shown in Figure 23.5 . Thus the reception margin in asynchronous mode is determined by formula (1) below.
1
 

M = 0.5 – ------- - – L 0.5 –
 
2N
M: Reception margin
N: Ratio of bit rate to clock
(N = 16 when SEMR.ABCS = 0, N = 8 when SEMR.ABCS = 1)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 13)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = {0.5 – 1/(2 × 16)} × 100 (%) = 46.875 (%)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
Note 1. This is an example when the ABCS bit in the SEMR register is 0. When the ABCS bit is 1, a frequency of 8 times
the bit rate is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base
clock.
Base clock
Receive data (RXDn)
Synchronization
sampling timing
Data sampling
timing
Figure 23.5 Receive Data Sampling Timing in Asynchronous Mode
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
D 0.5 –
 F   
-------------------- - 1
– + F 100
N
16 clock pulses
8 clock pulses
0 7
Start bit
23. Serial Communications Interface (SCIg, SCIh)
1
of the base clock, data is latched at the middle of each
(%) ··· Formula (1)
15 0
D0
1
the bit rate.
7 15
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0
D1