Operation Of Instructions; Data Prefetching By The Rmpa Instruction And The String-Manipulation Instructions; Pipeline; Overview - Renesas RX100 Series User Manual

RX13T Group
2.7

Operation of Instructions

2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation
Instructions
The RMPA instruction and the string-manipulation instructions except the SSTR instruction (that is, SCMPU, SMOVB,
SMOVF, SMOVU, SUNTIL, and SWHILE instructions) may prefetch data from the memory to speed up the read
processing. Data is prefetched from the prefetching start position with 3 bytes as the upper limit. The prefetching start
positions of each operation are shown below.
 RMPA instruction: The multiplicand address specified by R1, and the multiplier address specified by R2
 SCMPU instruction: The source address specified by R1 for comparison, and the destination address specified by
R2 for comparison
 SUNTIL and SWHILE instructions: The destination address specified by R1 for comparison
 SMOVB, SMOVF, and SMOVU instructions: The source address specified by R2 for transfer
2.8

Pipeline

2.8.1

Overview

The RX CPU has five-stage pipeline structure. The RX CPU instruction is converted into one or more micro-operations,
which are then executed in pipeline processing. In the pipeline stage, the IF stage is executed in the unit of instructions,
while the D and subsequent stages are executed in the unit of micro-operations.
The operation of pipeline and respective stages is described below.
(1) IF stage (instruction fetch stage)
In the IF stage, the CPU fetches instructions from the memory. As the RX CPU has four 4-byte instruction queues, it
fetches instructions until the instruction queue is full, regardless of the completion of decoding in the D (decoding) stage.
(2) D stage (decoding stage)
The CPU decodes instructions (DEC) in the D stage and converts them into micro-operations. The CPU reads the register
information (RF) in this stage and executes a bypass process (BYP) if the result of the preceding instruction will be used
in a subsequent instruction. The write of operation result to the register (RW) can be executed with the register reference
by using the bypass process.
(3) E stage (execution stage)
Operations and address calculations (OP) are processed in the E stage.
(4) M stage (memory access stage)
Operand memory accesses (OA1, OA2) are processed in the M stage. This stage is used only when the memory is
accessed, and is divided into two sub-stages, M1 and M2. The RX CPU enables respective memory accesses for M1 and
M2.
 M1 stage (memory-access stage 1)
Operand memory access (OA1) is processed.
Store operation: The pipeline processing ends when a write request is received via the bus.
Load operation: The operation proceeds to the M2 stage when a read request is received via the bus. If a request and
load data are received at the same timing (no-wait memory access), the operation proceeds to the WB stage.
 M2 stage (memory-access stage 2)
Operand memory access (OA2) is processed. The CPU waits for the load data in the M2 stage. When the load data
is received, the operation proceeds to the WB stage.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2. CPU
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