Register Descriptions; Interrupt Request Register N (Irn) (N = Interrupt Vector Number) - Renesas RX100 Series User Manual

RX13T Group
14.2

Register Descriptions

14.2.1

Interrupt Request Register n (IRn) (n = interrupt vector number)

Address(es): ICU.IR016 0008 7010h to ICU.IR255 0008 70FFh
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 IR Interrupt Status Flag
b7 to b1 — Reserved
Note 1. For an edge detection interrupt, only 0 can be written to this bit; do not write 1.
For a level detection interrupt, neither 0 nor 1 can be written.
IRn is provided for each interrupt source, where "n" indicates the interrupt vector number.
For the correspondence between interrupt sources and interrupt vector numbers, see Table 14.3, Interrupt Vector
Table .
IR Flag (Interrupt Status Flag)
This flag is the status flag of an individual interrupt request. This flag is set to 1 when the corresponding interrupt request
is generated. To detect an interrupt request, the interrupt request output should be enabled by the corresponding
peripheral module interrupt enable bit.
There are two interrupt request detection methods: edge detection and level detection. For interrupts from peripheral
modules, either edge detection or level detection is determined per interrupt source. For interrupts from IRQi (i = 0 to 5)
pins, edge detection or level detection is selected by setting the corresponding IRQCRi.IRQMD[1:0] bits. For detection
of the various interrupt sources, see Table 14.3, Interrupt Vector Table .
(1) Edge detection
[Setting condition]
 The flag is set to 1 in response to the generation of an interrupt request from the corresponding peripheral module or
IRQi pin. For interrupt generation by the various peripheral modules, refer to the sections describing the modules.
[Clearing conditions]
 The flag is cleared to 0 when the interrupt request destination accepts the interrupt request.
 The IR flag is cleared to 0 by writing 0 to it. Note, however, that writing 0 to the IR flag is prohibited if the
destination of the interrupt request is the DTC.
(2) Level detection
[Setting condition]
 The flag remains set to 1 while an interrupt request is being sent from the corresponding peripheral module or IRQi
pin. For interrupt generation by the various peripheral modules, refer to the sections describing the modules.
[Clearing condition]
 The flag is cleared to 0 when the source of the interrupt request is cleared (it is not cleared when the interrupt
request destination accepts the interrupt request). For clearing interrupts from the various peripheral modules, refer
to the sections describing the modules.
When level detection has been selected for an IRQi pin, the interrupt request is withdrawn by driving the IRQi pin high.
Do not write 0 or 1 to the IR flag while level detection is selected.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Description
0: No interrupt request is generated
1: An interrupt request is generated
These bits are read as 0. The write value should be 0.
b1 b0
— IR
0 0
14. Interrupt Controller (ICUb)
R/W
R/(W)
1
*
R/W
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