Chain Transfer - Renesas RX100 Series User Manual

RX13T Group
16.4.6

Chain Transfer

Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single transfer request.
If the MRB.CHNE bit is 1 and the MRB.CHNS bit is 0, an interrupt request to the CPU is not generated when the
specified number of data transfers is completed, or while the MRB.DISEL bit is 1 (an interrupt request to the CPU is
generated for every data transfer). Data transfer has no effect on the interrupt status flag, which is the request source.
The transfer information (SAR, DAR, CRA, CRB, MRA, MRB, and MRC) that define a data transfer can be specified
independently of each other. Figure 16.9 shows chain transfer operation.
DTC vector table
DTC vector
address
Start address of transfer
information
Figure 16.9 Chain Transfer Operation
If the MRB.CHNE bit is 1 and the CHNS bit is 1, chain transfer is performed only after completion of specified number
of data transfers. In repeat transfer mode, chain transfer is performed after completion of specified number of data
transfers.
For details on chain transfer conditions, refer to Table 16.4, Chain Transfer Conditions .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Transfer information
allocated in the RAM
Transfer information
CHNE bit = 1
Transfer information
CHNE bit = 0
16. Data Transfer Controller (DTCb)
Data area
Transfer source data (1)
Transfer destination data (1)
Transfer source data (2)
Transfer destination data (2)
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