Renesas RX100 Series User Manual page 199

RX13T Group
Interrupt controller
Voltage monitoring 2 interrupt
Voltage monitoring 1 interrupt
IWDT underflow/refresh error
Oscillation stop detection interrupt
NMI pin Digital filter
NM
IFLTE
IRQ0
IRQ5
Peripheral
module
Figure 14.1 Block Diagram of Interrupt Controller
Table 14.2 lists the input/output pins of the interrupt controller.
Table 14.2 Pin Configuration of Interrupt Controller
Pin Name
NMI
IRQ0 to IRQ5
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
NMI
SR
Detection
NM NMI NMI NMI
IFLTC CR CLR ER
IRQFLTE IRQFLTC
IRQCR
0 0
Digital filter Detection
IRQ0 to IRQ5 detection
Interrupt source
NMIER : Non-maskable interrupt enable register
NMICR : NMI pin interrupt control register
: Non-maskable interrupt status clear register
NMICLR
NMISR : Non-maskable interrupt status register
IRQCR : IRQ control register
I/O
Input
Input
Clock
restoration
judgment
Module data bus
DTCER
IR clear
IER cntl
Clear
IR
Destination
switchover to CPU
Interrupt status, destination switchover
IR : Interrupt request register
IER : Interrupt request enable register
IPR : Interrupt source priority register
FIR : Fast interrupt set register
DTCER : DTC transfer request enable register
Description
Non-maskable interrupt request pin
External interrupt request pins
14. Interrupt Controller (ICUb)
Clock restoration request
Clock restoration enable level
Non-maskable interrupt request
IPR FIR
Interrupt request
CPU priority level
Interrupt acceptance
judgment
DTC
transfer request
DTC
start control DTC response
IR clear
IRQFLTE0 : IRQ pin digital filter enable register 0
IRQFLTC0 : IRQ pin digital filter setting register 0
NMIFLTE : NMI pin digital filter enable register
NMIFLTC : NMI pin digital filter setting register
Page 199 of 1041
Clock
generation
circuit
CPU
DTC