Port Output Enable 3 (Poe3C); Overview - Renesas RX100 Series User Manual

RX13T Group
20.

Port Output Enable 3 (POE3C)

This MCU incorporates a port output enable 3 (POE3C) which can be used to, under various conditions, disable output
signals for the MTU. Every output signal is put in the high-impedance state when the output is disabled.
In this section, "PCLK" is used to refer to PCLKB.
20.1

Overview

Table 20.1 lists the specifications of the POE, and Figure 20.1 shows a block diagram of the POE.
Table 20.1 POE Specifications
Item
Pin status while output is
disabled
Target pins for switching
to high-impedance state
Generating conditions of
request for switching to
high-impedance state
Function
The POE has input-level detection circuits, output-level comparison circuits, and a high-impedance request/interrupt
request generating circuit as shown in Figure 20.1 .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
 High-impedance
 MTU output pins
MTU0 pins (MTIOC0A, MTIOC0B, MTIOC0C, MTIOC0D)
MTU3 pins (MTIOC3B, MTIOC3D)
MTU4 pins (MTIOC4A, MTIOC4B, MTIOC4C, MTIOC4D)
 Input signal detection: Detection of the POE0#, POE8#, and POE10# signal level.
 Simultaneous conduction between output pins: A match (simultaneous conduction) between the output
signal levels at the active level over one or more cycles on the following combination of pins
MTU Complementary PWM Output Pins
1 MTIOC3B and MTIOC3D
2 MTIOC4A and MTIOC4C
3 MTIOC4B and MTIOC4D
 The SPOER register setting
 Detection that the main clock oscillator had stopped oscillating
 Detection of the comparator C (CMPC) outputs
 Each of the POE0#, POE8#, and POE10# input pins can be set for falling edge, PCLK/8 × 16, PCLK/16 ×
16, or PCLK/128 × 16 low-level sampling.
 The outputs of the target pins can be in the high-impedance state by falling-edge or low-level sampling of
the POE0#, POE8#, or POE10# pin.
 The outputs of the target pins can be in the high-impedance state when oscillation stop is detected by the
oscillation stop detection function of the clock generator.
 The MTU complementary PWM outputs can be in the high-impedance state when output levels of the
MTU complementary PWM output pins are compared and simultaneous active-level output continues for
one cycle or more.
 The outputs of the target pins can be in the high-impedance state in response to comparator C (CMPC)
output detection.
 The outputs of the target pins can be in the high-impedance state by modifying the settings of the POE
registers.
 Interrupts can be generated by input-level sampling or output-level comparison results.
20. Port Output Enable 3 (POE3C)
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