Renesas RX100 Series User Manual page 457

RX13T Group
(4) Complementary PWM Mode Output Protection Functions
The following output protection functions are provided for complementary PWM mode.
(a) Register and Counter Miswrite Prevention Function
Access from the CPU to the mode registers, control registers, compare registers, and counters can be enabled or disabled
by setting the RWE bit in the TRWERA register. The applicable registers are some of the registers in MTU3 and MTU4
shown below:
24 registers in total
MTU3.TCR, MTU4.TCR, MTU3.TCR2, MTU4.TCR2, MTU3.TMDR1, MTU4.TMDR1, MTU3.TIORH,
MTU4.TIORH, MTU3.TIORL, MTU4.TIORL, MTU3.TIER, MTU4.TIER, MTU3.TCNT, MTU4.TCNT,
MTU3.TGRA, MTU4.TGRA, MTU3.TGRB, MTU4.TGRB, MTU.TOERA, MTU.TOCR1A, MTU.TOCR2A,
MTU.TGCRA, MTU.TCDRA, and MTU.TDDRA
This function can disable CPU access to the mode registers, control registers, and counters to prevent miswriting due to
CPU runaway. In the access-disabled state, the applicable registers are read as undefined and writing to these registers is
ignored.
(b) Halting of PWM Output by External Signal
The PWM output pins of MTU0, MTU3, and MTU4 can be set to the high-impedance state automatically.
Refer to section 20, Port Output Enable 3 (POE3C) , for details.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Page 457 of 1041