Interrupts In Simple I C Mode - Renesas RX100 Series User Manual

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23.12.4
Interrupts in Simple I
The interrupt sources in simple I
interrupt (TEI) request. The receive error interrupt (ERI) request cannot be used.
The DTC can also be used to handle transfer in simple I
When the value of the IICINTM bit in the SIMR2 register is 1, an RXI request will be generated on the falling edge of
the SSCLn signal for the eighth bit. If the RXI has been set up as an activating request for the DTC beforehand, the RXI
request will activate the DTC to handle transfer of the received data. Furthermore, a TXI request is generated on the
falling edge of the SSCLn signal for the ninth bit (acknowledge bit). If the TXI has been set up as an activating request
for the DTC beforehand, the TXI request will activate the DTC to handle transfer of the transmit data.
When the value of the IICINTM bit in the SIMR2 register is 0, an RXI request (ACK detection) if the input on the
SSDAn pin is at the low level or a TXI request (NACK detection) if the input on the SSDAn pin is at the high level will
be generated on the rising edge of the SSCLn signal for the ninth bit (acknowledge bit). If the RXI has been set up as an
activating request for the DTC beforehand, the RXI request will activate the DTC to handle transfer of the received data.
Also, if the DTC is used for data transfer in reception or transmission, be sure to set up and enable the DTC before setting
up the SCI.
When the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits in the SIMR3 register are used to generate a start condition,
restart condition, or stop condition, the STI request is issued when generation is complete.
Table 23.33
SCI Interrupt Sources
Interrupt Source
Name
IICINTM bit = 0
RXI
ACK detection
TXI
NACK detection
STI
Completion of generation of a start,
restart, or stop condition
Note 1. Activation of the DTC is only possible when the SIMR2.IICINTM bit is 1 (use reception and transmission interrupts).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
2
C Mode
2
C mode are listed in Table 23.33 . The STI interrupt is allocated to the transmit end
IICINTM bit = 1
Interrupt Flag
Reception
Transmission
IICSTIF
23. Serial Communications Interface (SCIg, SCIh)
2
C mode.
DTC Activation
Possible
1
Possible*
Not possible
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