Renesas RX100 Series User Manual page 528

RX13T Group
MTIOC3B
Input signals for use in
MTIOC3D
control of complementary
MTIOC4A
PWM output from the MTU
MTIOC4C
pins (MTU3 and MTU4)
MTIOC4B
MTIOC4D
POE0#
MTU (MTU3 and MTU4)
input signal
POE8#
MTU (MTU0) input signal
POE10#
Comparator output signal
Main clock oscillation stop detection signal
Figure 20.1 POE Block Diagram
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Output-level
comparison circuit
Output-level
comparison circuit
Output-level
comparison circuit
ALR1
Input-level detection circuit
I/O register setting
Falling edge detection
circuit
Function select
register setting
Low-level sampling
circuit
1
Input-level detection circuit
I/O register setting
Falling edge detection
Function select circuit
register setting
Low-level sampling
circuit
1
Input-level detection circuit
I/O register setting
Falling edge detection
Function select
circuit
register setting
Low-level sampling
circuit
1
POECMPFR
POECMPSEL
20. Port Output Enable 3 (POE3C)
POECR1 to
POECR5
PCLK/8
SPOER
PCLK/16
PCLK/128
Divider
PCLK
High-impedance request signal or
interrupt request signal (OEI1) for
the MTU complementary PWM
output pins (MTU3 and MTU4)
High-impedance request signal or
interrupt request signal (OEI3) for
MTU0 pin
Interrupt request signal (OEI4)
Page 528 of 1041