Renesas RX100 Series User Manual page 262

RX13T Group
DTC vector base address
Vector address = DTCVBR + vector number × 4
Figure 16.3 DTC Vector Table and Transfer Information
Allocation of transfer information in
short-address mode
Lower address
( ): Lower address to be allocated
in the big-endian area
Start address
3 (0) 2 (1)
MRA
MRB
CRA
Chain
transfer
MRA
MRB
CRA
Figure 16.4 Allocation of Transfer Information in the RAM Area
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
DTC vector table
Start address of
transfer information 0
+4
Start address of
transfer information 1
+8
Start address of
transfer information 2
+4n
Start address of
transfer information n
4 bytes
1 (2) 0 (3)
SAR
Transfer information
DAR
per transfer
(12 bytes)
CRB
SAR
Transfer information
for the second
DAR transfer in chain
transfer mode
(12 bytes)
CRB
4 bytes
16. Data Transfer Controller (DTCb)
Allocation of transfer information in
full-address mode
Lower address
( ): Lower address to be allocated
in the big-endian area
Start address
3 (0) 2 (1)
MRA MRB
SAR
DAR
CRA
Chain
transfer
MRA MRB
SAR
DAR
CRA
4 bytes
Transfer information 0
Transfer information 1
Transfer information n
4 bytes
1 (2) 0 (3)
Reserved
MRC
(00h)
Transfer information
per transfer
(16 bytes)
CRB
Reserved
MRC
(00h)
Transfer information
for the second
transfer in chain
transfer mode
(16 bytes)
CRB
Page 262 of 1041