Voltage Monitoring 2 Circuit Status Register (Lvd2Sr) - Renesas RX100 Series User Manual

RX13T Group
8.2.4

Voltage Monitoring 2 Circuit Status Register (LVD2SR)

Address(es): 0008 00E3h
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 LVD2DET Voltage Monitoring 2 Voltage Change
Detection Flag
b1 LVD2MON Voltage Monitoring 2 Signal Monitor Flag
b7 to b2 — Reserved
Note: Set the PRCR.PRC3 bit to 1 (write enabled) before rewriting this register.
Note 1. Only 0 can be written to this bit. After writing 0 to this bit, it takes two system clock cycles for the bit to be read as 0.
LVD2DET Flag (Voltage Monitoring 2 Voltage Change Detection Flag)
The LVD2DET flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.LVD2CMPE bit is 1 (voltage monitoring 2 circuit comparison result output enabled).
The LVD2DET flag should be set to 0 after LVD2CR0.LVD2RIE is set to 0 (disabled). LVD2CR0.LVD2RIE can be set
to 1 (enabled) again after a period of two or more cycles of PCLKB has elapsed.
With read access to an I/O register which access cycle number is defined by PCLKB, two or more cycles of PCLKB may
have to be secured as waiting time.
LVD2MON Flag (Voltage Monitoring 2 Signal Monitor Flag)
The LVD2MON flag is enabled when the LVCMPCR.LVD2E bit is 1 (voltage detection 2 circuit enabled) and the
LVD2CR0.LVD2CMPE bit is 1 (voltage monitoring 2 circuit comparison result output enabled).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
LVD2M
— — — —
0 0 0 0
b1 b0
LVD2D
ON ET
1 0
Description
0: Not detected
1: Vdet2 passage detection
0: VCC < Vdet2
1: VCC ≥ Vdet2 or LVD2MON is disabled
These bits are read as 0. The write value should be 0.
8. Voltage Detection Circuit (LVDAb)
Page 118 of 1041
R/W
R/(W)
1
*
R
R/W