I 2 C-Bus Mode Register 3 (Icmr3) - Renesas RX100 Series User Manual

RX13T Group
2
24.2.5 I C-bus Mode Register 3 (ICMR3)
Address(es): RIIC0.ICMR3 0008 8304h
b7 b6
WAIT RDRFS ACKW
SMBS
0 0
Value after reset:
Bit Symbol Bit Name
b1, b0 NF[1:0] Noise Filter Stage Select
b2 ACKBR Receive Acknowledge
b3 ACKBT Transmit Acknowledge
b4 ACKWP ACKBT Write Protect
b5 RDRFS RDRF Flag Set Timing
Select
b6 WAIT WAIT
b7 SMBS SMBus/I
Note 1. Write to the ACKBT bit only while the ACKWP bit is already 1. If it is attempted to write 1 to both the ACKWP and ACKBT bits at
the same time, the ACKBT bit will not be set to 1.
Note 2. The WAIT and RDRFS bits are valid only in receive mode (invalid in transmit mode).
NF[1:0] Bits (Noise Filter Stage Select)
These bits are used to select the number of stages in the digital noise filter.
For details on the digital noise filter function, refer to section 24.6, Digital Noise Filter Circuit .
Note: Set the noise range to be filtered out by the noise filter within a range less than the SCL0 line high-level period or
low-level period. If the noise filter width is set to a value of [the shorter one of either SCL high width or SCL low
width] – {1.5 × t
IICcyc
analog noise filter, a reference value)} or a greater value, the SCL clock is regarded as noise by the noise filter
function of the RIIC, which may prevent the RIIC from operating normally.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
ACKBT ACKBR
P
0 0 0 0
Description
b1 b0
0 0: Noise of up to one IICφ cycle is filtered out (single-stage filter).
0 1: Noise of up to two IICφ cycles is filtered out (2-stage filter).
1 0: Noise of up to three IICφ cycles is filtered out (3-stage filter).
1 1: Noise of up to four IICφ cycles is filtered out (4-stage filter).
0: 0 is received as the acknowledge bit (ACK reception).
1: 1 is received as the acknowledge bit (NACK reception).
0: 0 is sent as the acknowledge bit (ACK transmission).
1: 1 is sent as the acknowledge bit (NACK transmission).
0: Modification of the ACKBT bit is disabled.
1: Modification of the ACKBT bit is enabled.
0: The RDRF flag is set at the rising edge of the ninth SCL clock cycle.
(The SCL0 line is not held low at the falling edge of the eighth clock
cycle.)
1: The RDRF flag is set at the rising edge of the eighth SCL clock cycle.
(The SCL0 line is held low at the falling edge of the eighth clock cycle.)
Low-hold is released by writing a value to the ACKBT bit.
0: No WAIT
(The period between ninth clock cycle and first clock cycle is not held
low.)
1: WAIT
(The period between ninth clock cycle and first clock cycle is held low.)
Low-hold is released by reading the ICDRR register.
2 2
C-bus Select 0: The I C-bus is selected.
1: The SMBus is selected.
(cycle time of internal reference clock (IICφ)) + 120 ns (pulse width suppressed by the
b1 b0
NF[1:0]
0 0
2
24. I C-bus Interface (RIICa)
R/W
R/W
R
R/W*
R/W*
R/W*
R/W*
R/W
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