Phase Counting Mode; 16-Bit Phase Counting Mode - Renesas RX100 Series User Manual

RX13T Group
19.3.6

Phase Counting Mode

There are two phase counting modes: 16-bit phase counting mode in which MTU1 and MTU2 operate independently,
and cascade connection 32-bit phase counting mode in which MTU1 and MTU2 are cascaded.
In phase counting mode, the phase difference between two external input clocks is detected and the corresponding TCNT
is incremented or decremented.
Two external clock input pins for each phase counting mode are not affected by the settings of TCR.TPSC[2:0],
TCR2.TPSC2[2:0], and CKEG[1:0]. The two external clock input pins used in 16-bit phase counting mode and cascade
connection 32-bit phase counting mode of MTU2 can be selected by MTU1.TMDR3.PHCKSEL. In a phase counting
mode other than 16-bit phase counting mode and cascade connection 32-bit phase counting mode of MTU2, MTCLKA
and MTCLKB are selected for A-phase and B-phase, respectively. In phase counting mode, the external clock pins
MTCLKA, MTCLKB, MTCLKC, and MTCLKD are used for two-phase encoder pulse input.
Table 19.50 lists the external clock input pins to be connected in each phase counting mode.
Table 19.50 Clock Input Pins in Phase Counting Mode
Phase Counting Mode
MTU1 16-bit phase counting mode
MTU2 16-bit phase counting mode
Cascade connection 32-bit phase counting mode
19.3.6.1

16-Bit Phase Counting Mode

When the MTU1.TMDR3.LWA is 0, 16-bit phase counting mode can be set individually for MTU1 and MTU2.
In 16-bit phase counting mode, the phase difference between two external input clocks is detected and the 16-bit counter
TCNT of the corresponding channel is incremented or decremented.
When 16-bit phase counting mode is specified, an external clock is selected as the count clock and TCNT operates as an
up-counter/down-counter regardless of the setting of TCR.TPSC[2:0], TCR2.TPSC2[2:0], and CKEG[1:0]. However,
the functions of TCR.CCLR[1:0],TIOR, TIER, and TGR are enabled, and input capture/compare match and interrupt
functions can be used.
These external input pins can be used for two-phase encoder pulse input.
When an overflow occurs while TCNT is counting up and the corresponding TIER.TCIEV bit is 1, a TCIV interrupt is
generated. When an underflow occurs while TCNT is counting down and the corresponding TIER.TCIEU bit is 1, a
TCIU interrupt is generated.
The TSR.TCFD flag is the count direction flag. Read the TCFD flag to check whether TCNT is counting up and down.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
TMDR3.PHCKSEL bit
x (Don't care)
0
1 (initial value)
0
1 (initial value)
External Clock Input Pins
A-Phase B-Phase
MTCLKA MTCLKB
MTCLKA MTCLKB
MTCLKC MTCLKD
MTCLKA MTCLKB
MTCLKC MTCLKD
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