Non-Maskable Interrupt Status Clear Register (Nmiclr) - Renesas RX100 Series User Manual

RX13T Group
14.2.12

Non-Maskable Interrupt Status Clear Register (NMICLR)

Address(es): ICU.NMICLR 0008 7582h
b7 b6
— —
Value after reset: 0 0
Bit Symbol
b0 NMICLR
b1 OSTCLR
b2 —
b3 IWDTCLR
b4 LVD1CLR
b5 LVD2CLR
b7, b6 —
Note 1. Only 1 can be written to this bit.
NMICLR Bit (NMI Clear)
Writing 1 to the NMICLR bit clears the NMISR.NMIST flag. This bit is read as 0.
OSTCLR Bit (OST Clear)
Writing 1 to the OSTCLR bit clears the NMISR.OSTST flag. This bit is read as 0.
IWDTCLR Bit (IWDT Clear)
Writing 1 to the IWDTCLR bit clears the NMISR.IWDTST flag. This bit is read as 0.
LVD1CLR Bit (LVD1 Clear)
Writing 1 to the LVD1CLR bit clears the NMISR.LVD1ST flag. This bit is read as 0.
LVD2CLR Bit (LVD2 Clear)
Writing 1 to the LVD2CLR bit clears the NMISR.LVD2ST flag. This bit is read as 0.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
LVD2C LVD1C IWDTC
—
LR LR LR
0 0 0 0
Bit Name Description
NMI Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.NMIST flag.
Writing 0 to this bit has no effect.
OST Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.OSTST flag.
Writing 0 to this bit has no effect.
Reserved This bit is read as 0. The write value should be 0.
IWDT Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.IWDTST
flag. Writing 0 to this bit has no effect.
LVD1 Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.LVD1ST flag.
Writing 0 to this bit has no effect.
LVD2 Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.LVD2ST flag.
Writing 0 to this bit has no effect.
Reserved These bits are read as 0. The write value should be 0.
b1 b0
OSTCL NMICL
R R
0 0
14. Interrupt Controller (ICUb)
R/W
R/(W)
* 1
R/(W)
1
*
R/W
R/(W)
1
*
R/(W)
1
*
R/(W)
* 1
R/W
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