Note On Transition From Normal Mode Or Pwm Mode 1 To Reset-Synchronized Pwm Mode; Output Level In Complementary Pwm Mode And Reset-Synchronized Pwm Mode; Simultaneous Input Capture In Mtu1.Tcnt And Mtu2.Tcnt In Cascade Connection - Renesas RX100 Series User Manual

RX13T Group
19.6.19 Note on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized
PWM Mode
When making a transition from normal mode or PWM mode 1 to reset-synchronized PWM mode in MTU3 and MTU4,
if the counter is stopped while the output pins (MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B and
MTIOC4D) are held at a high level and then operation is started after a transition to reset-synchronized PWM mode, the
initial pin output will not be correct.
When making a transition from normal mode to reset-synchronized PWM mode, write 11h to MTU3.TIORH,
MTU3.TIORL, MTU4.TIORH, and MTU4.TIORL to initialize the output pin state to a low level, then set the registers to
the initial value (00h) before making the mode transition.
When making a transition from PWM mode 1 to reset-synchronized PWM mode, switch to normal mode, initialize the
output pin state to a low level, and then set the registers to the initial value (00h) before making the transition to reset-
synchronized PWM mode.
19.6.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM
Mode
When MTU3 and MTU4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform
output level is determined by the OLSP and OLSN bits in the timer output control register (TOCR1A). In
complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to 00h.
The output level in negative phase when the TDERA.TDER bit is set to 0 in complementary PWM mode (the dead time
is not generated) does not depend on the setting of the TOCR1A.OLSN bit. It is equivalent to the inverted level of
positive phase output based on the setting of the TOCR1A.OLSP bit.
19.6.21 Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade
Connection
When timer counters 1 and 2 (MTU1.TCNT and MTU2.TCNT) operate as a 32-bit counter in cascade connection, the
cascaded counter value cannot be captured successfully in some cases even if input-capture input is simultaneously done
to MTIOC1A and MTIOC2A or to MTIOC1B and MTIOC2B. This is because the input timing of MTIOC1A and
MTIOC2A or to MTIOC1B and MTIOC2B may not be the same when external input-capture signals input into
MTU1.TCNT and MTU2.TCNT are taken in synchronization with the internal clock.
For example, MTU1.TCNT (the counter for upper 16 bits) does not capture the count-up value by an overflow from
MTU2.TCNT (the counter for lower 16 bits) but captures the count value before the up-counting. In this case, the values
of MTU1.TCNT = FFF1h and MTU2.TCNT = 0000h should be transferred to MTU1.TGRA and MTU2.TGRA or to
MTU1.TGRB and MTU2.TGRB, but the values of MTU1.TCNT = FFF0h and MTU2.TCNT = 0000h are erroneously
transferred.
The MTU has a function that allows simultaneous capture of MTU1.TCNT and MTU2.TCNT with a single input capture
input. This function can be used to read the 32-bit counter such that MTU1.TCNT and MTU2.TCNT are captured at the
same time. For details, refer to section 19.2.11, Timer Input Capture Control Register (TICCR) .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
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