Oscillation Stop Detection Control Register (Ostdcr) - Renesas RX100 Series User Manual

RX13T Group
9.2.10

Oscillation Stop Detection Control Register (OSTDCR)

Address(es): 0008 0040h
b7 b6
OSTDE —
0 0
Value after reset:
Bit Symbol Bit Name
b0 OSTDIE Oscillation Stop Detection
Interrupt Enable
b6 to b1 — Reserved
b7 OSTDE Oscillation Stop Detection
Function Enable
Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
OSTDIE Bit (Oscillation Stop Detection Interrupt Enable)
If the oscillation stop detection flag in the oscillation stop detection status register (OSTDSR.OSTDF) requires clearing,
do this after setting the OSTDIE bit to 0. Wait for at least two cycles of PCLKB before again setting the OSTDIE bit to 1.
According to the number of cycles for access to read a given I/O register, wait time longer than two cycles of PCLKB
may have to be secured.
OSTDE Bit (Oscillation Stop Detection Function Enable)
This bit enables or disables the oscillation stop detection function.
When the OSTDE bit is 1 (oscillation stop detection function enabled), the LOCO stop bit (LOCOCR.LCSTP) is set to 0
and the LOCO operation is started. The LOCO cannot be stopped while the oscillation stop detection function is enabled;
writing 1 (LOCO is stopped) to the LOCOCR.LCSTP bit is invalid.
When the oscillation stop detection flag in the oscillation stop detection status register (OSTDSR.OSTDF) is 1 (main
clock oscillation stop has been detected), writing 0 to the OSTDE bit is invalid.
When the OSTDE bit is 1, a transition cannot be made to software standby mode. To make a transition to software
standby mode, execute the WAIT instruction with the OSTDE bit being 0.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Description
0: The oscillation stop detection interrupt is disabled. Oscillation stop
detection is not notified to the POE.
1: The oscillation stop detection interrupt is enabled. Oscillation stop
detection is notified to the POE.
These bits are read as 0. The write value should be 0.
0: Oscillation stop detection function is disabled.
1: Oscillation stop detection function is enabled.
b1 b0
OSTDI
—
E
0 0
9. Clock Generation Circuit
R/W
R/W
R/W
R/W
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