Renesas RX100 Series User Manual page 25

32-bit mcu
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26.2.6
A/D Channel Select Register C0 (ADANSC0) ........................................................................ 821
26.2.7
26.2.8
26.2.9
A/D Control Extended Register (ADCER) .............................................................................. 824
26.2.10
A/D Conversion Start Trigger Select Register (ADSTRGR) ................................................... 826
26.2.11
A/D Conversion Extended Input Control Register (ADEXICR) ............................................. 828
26.2.12
A/D Group C Trigger Select Register (ADGCTRGR) ............................................................. 829
26.2.13
A/D Sampling State Register n (ADSSTRn) (n = 0 to 7, O) .................................................... 831
26.2.14
A/D Sample-and-Hold Circuit Control Register (ADSHCR) .................................................. 832
26.2.15
A/D Disconnection Detection Control Register (ADDISCR) .................................................. 833
26.2.16
A/D Group Scan Priority Control Register (ADGSPCR) ........................................................ 834
26.2.17
A/D Programmable Gain Amplifier Control Register (ADPGACR) ....................................... 836
26.2.18
26.3
Operation ........................................................................................................................................... 838
26.3.1
Scanning Operation .................................................................................................................. 838
26.3.2
Single Scan Mode ..................................................................................................................... 839
26.3.2.1
26.3.2.2
26.3.2.3
(Without Channel-Dedicated Sample-and-Hold Circuits) .............................................. 841
26.3.2.4
(With Channel-Dedicated Sample-and-Hold Circuits) ................................................... 842
26.3.2.5
A/D Conversion of Internal Reference Voltage .............................................................. 843
26.3.2.6
A/D Conversion in Double Trigger Mode ....................................................................... 844
26.3.2.7
A/D Conversion in Extended Double Trigger Mode ...................................................... 845
26.3.3
Continuous Scan Mode ............................................................................................................. 847
26.3.3.1
26.3.3.2
26.3.3.3
(Without Channel-Dedicated Sample-and-Hold Circuits) .............................................. 849
26.3.3.4
(With Channel-Dedicated Sample-and-Hold Circuits) ................................................... 850
26.3.4
Group Scan Mode ..................................................................................................................... 851
26.3.4.1
Basic Operation ............................................................................................................... 851
26.3.4.2
A/D Conversion in Double Trigger Mode ....................................................................... 852
26.3.4.3
Operation under Group Priority Control ......................................................................... 854
26.3.5
Analog Input Sampling Time and Scan Conversion Time ....................................................... 872
26.3.6
Usage Example of A/D Data Register Automatic Clearing Function ...................................... 875
26.3.7
A/D-Converted Value Addition/Average Mode ....................................................................... 875
26.3.8
Disconnection Detection Assist Function ................................................................................. 875
26.3.9
Starting A/D Conversion with Asynchronous Trigger ............................................................. 877
26.3.10

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