Iwdt Count Stop Control Register (Iwdtcstpr); Option Function Select Register 0 (Ofs0) - Renesas RX100 Series User Manual

RX13T Group
22.2.5

IWDT Count Stop Control Register (IWDTCSTPR)

Address(es): IWDT.IWDTCSTPR 0008 8038h
b7 b6
SLCST
—
P
Value after reset: 1 0
Bit Symbol
b6 to b0 —
b7 SLCSTP
The IWDTCSTPR register controls whether to stop the IWDT counter in a low power consumption state. There are some
restrictions on writing to the IWDTCSTPR register. For details, refer to section 22.3.2, Control over Writing to the
IWDTCR, IWDTRCR, and IWDTCSTPR Registers .
In auto-start mode, the IWDTCSTPR register setting are disabled, and the settings in option function select register 0
(OFS0) are enabled. The bit setting mode to the IWDTCSTPR register can also be made in the OFS0 register. For details,
refer to section 22.3.8, Correspondence between Option Function Select Register 0 (OFS0) and IWDT
Registers .
SLCSTP Bit (Sleep Mode Count Stop Control)
This bit selects whether to stop counting at a transition to sleep mode, software standby mode, or deep sleep mode.
22.2.6

Option Function Select Register 0 (OFS0)

For option function select register 0 (OFS0), refer to section 22.3.8, Correspondence between Option Function
Select Register 0 (OFS0) and IWDT Registers .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Bit Name
Reserved
Sleep Mode Count Stop Control
22. Independent Watchdog Timer (IWDTa)
b1 b0
— —
0 0
Description
These bits are read as 0. Writing to these bits has no effect.
0: Count stop is disabled.
1: Count is stopped at a transition to sleep mode, software
standby mode, or deep sleep mode.
R/W
R
R/W
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