Data Types; Endian; Switching The Endian - Renesas RX100 Series User Manual

RX13T Group
2.4

Data Types

The RX CPU can handle four types of data: integer, floating-point, bit, and string.
For details, refer to RX Family User's Manual: Software.
2.5

Endian

For the RX CPU, instructions are little endian, but the data arrangement is selectable as little or big endian.
2.5.1

Switching the Endian

As arrangements of bytes, this MCU supports both big endian, where the higher-order byte (MSB) is at location 0, and
little endian, where the lower-order byte (LSB) is at location 0.
For details on the endian setting, refer to section 3, Operating Modes.
Operations for access differ according to the endian setting and, depending on the instruction, whether 8-, 16- or 32-bit
access has been selected. Operations for access in the various possible cases are described in Table 2.1 to Table 2.12.
In the tables,
LL indicates bits D7 to D0 of the general-purpose register,
LH indicates bits D15 to D8 of the general-purpose register,
HL indicates bits D23 to D16 of the general-purpose register, and
HH indicates bits D31 to D24 of the general-purpose register.
General purpose register: Rm
Table 2.1 32-Bit Read Operations when Little Endian has been Selected
Operation
Reading a 32-bit unit
Address of src from address 0
Address 0 Transfer to LL
Address 1 Transfer to LH
Address 2 Transfer to HL
Address 3 Transfer to HH
Address 4
Address 5
Address 6
Address 7
Table 2.2 32-Bit Read Operations when Big Endian has been Selected
Operation
Reading a 32-bit unit
Address of src from address 0
Address 0 Transfer to HH
Address 1 Transfer to HL
Address 2 Transfer to LH
Address 3 Transfer to LL
Address 4
Address 5
Address 6
Address 7
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
D31 to D24
HH
Reading a 32-bit unit
from address 1
—
Transfer to LL
Transfer to LH
Transfer to HL
— Transfer to HH
— —
— —
— —
Reading a 32-bit unit
from address 1
—
Transfer to HH
Transfer to HL
Transfer to LH
— Transfer to LL
— —
— —
— —
D23 to D16 D15 to D8
HL LH
Reading a 32-bit unit Reading a 32-bit unit
from address 2 from address 3
—
—
Transfer to LL
Transfer to LH Transfer to LL
Transfer to HL Transfer to LH
Transfer to HH Transfer to HL
— Transfer to HH
—
Reading a 32-bit unit Reading a 32-bit unit
from address 2 from address 3
—
—
Transfer to HH
Transfer to HL Transfer to HH
Transfer to LH Transfer to HL
Transfer to LL Transfer to LH
— Transfer to LL
—
2. CPU
D7 to D0
LL
Reading a 32-bit unit
from address 4
— —
— —
— —
—
Transfer to LL
Transfer to LH
Transfer to HL
— Transfer to HH
Reading a 32-bit unit
from address 4
— —
— —
— —
—
Transfer to HH
Transfer to HL
Transfer to LH
— Transfer to LL
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