Serial Mode Register (Smr) - Renesas RX100 Series User Manual

RX13T Group
23.2.7

Serial Mode Register (SMR)

Note: Some bits in SMR have different functions in smart card interface mode and non-smart card interface mode.
(1) Non-Smart Card Interface Mode (SCMR.SMIF = 0)
Address(es): SCI1.SMR 0008 A020h, SCI5.SMR 0008 A0A0h, SCI12.SMR 0008 B300h
b7 b6
CM CHR
Value after reset: 0 0
Bit Symbol Bit Name
b1, b0 CKS[1:0] Clock Select
b2 MP Multi-Processor Mode
b3 STOP Stop Bit Length
b4 PM Parity Mode
b5 PE Parity Enable
b6 CHR Character Length
b7 CM Communications Mode
Note 1. n is the decimal notation of the value of n in the BRR register (refer to section 23.2.11, Bit Rate Register (BRR)).
Note 2. In other than asynchronous mode, this bit setting is invalid and a fixed data length of 8 bits is used.
Note 3. LSB first is fixed and the MSB (bit 7) in the TDR register is not transmitted in transmission.
Note 4. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
CKS[1:0] Bits (Clock Select)
These bits select the clock source for the on-chip baud rate generator.
For the relation between the settings of these bits and the baud rate, refer to section 23.2.11, Bit Rate Register (BRR) .
MP Bit (Multi-Processor Mode)
Disables/enables the multi-processor communications function. The settings of the PE bit and PM bit are invalid in
multi-processor mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
PE PM STOP MP
0 0 0 0
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
CKS[1:0]
0 0
Description
b1 b0
1
0 0: PCLK (n = 0)*
1
0 1: PCLK/4 (n = 1)*
1
1 0: PCLK/16 (n = 2)*
1
1 1: PCLK/64 (n = 3)*
(Valid only in asynchronous mode)
0: Multi-processor communications function is disabled
1: Multi-processor communications function is enabled
(Valid only in asynchronous mode)
0: 1 stop bit
1: 2 stop bits
(Valid only when the PE bit is 1)
0: Selects even parity
1: Selects odd parity
(Valid only in asynchronous mode)
 When transmitting
0: Parity bit addition is not performed
1: The parity bit is added
 When receiving
0: Parity bit checking is not performed
1: The parity bit is checked
(Valid only in asynchronous mode*
Selects in combination with the SCMR.CHR1 bit.
CHR1 CHR
0 0: Transmit/receive in 9-bit data length
0 1: Transmit/receive in 9-bit data length
1 0: Transmit/receive in 8-bit data length (initial value)
1 1: Transmit/receive in 7-bit data length*
0: Asynchronous mode or simple I
1: Clock synchronous mode or simple SPI mode
2
)
3
2
C mode
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