I 2 C Mode Register 2 (Simr2) - Renesas RX100 Series User Manual

RX13T Group
2
23.2.16 I C Mode Register 2 (SIMR2)
Address(es): SCI1.SIMR2 0008 A02Ah, SCI5.SIMR2 0008 A0AAh, SCI12.SIMR2 0008 B30Ah
b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
2
b0 IICINTM I C Interrupt Mode Select
b1 IICCSC Clock Synchronization
b4 to b2 — Reserved
b5 IICACKT ACK Transmission Data
b7, b6 — Reserved
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (serial reception and transmission disabled).
SIMR2 is used to select how reception and transmission are controlled in simple I
2
IICINTM Bit (I C Interrupt Mode Select)
This bit selects the sources of interrupt requests in simple I
IICCSC Bit (Clock Synchronization)
Set the IICCSC bit to 1 if the internally generated SSCLn clock signal is to be synchronized when the SSCLn pin has
been placed at the low level in the case of a wait inserted by the other device, etc.
The SSCLn clock signal is not synchronized if the IICCSC bit is 0. The SSCLn clock signal is generated in accord with
the rate selected in the BRR regardless of the level being input on the SSCLn pin.
Set the IICCSC bit to 1 except during debugging.
IICACKT Bit (ACK Transmission Data)
Transmitted data contains ACK bits. Set this bit to 1 when ACK and NACK bits are received.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
IICACK
— — —
T
0 0 0 0
Description
0: Use ACK/NACK interrupts.
1: Use reception and transmission interrupts.
0: No synchronization with the clock signal
1: Synchronization with the clock signal
These bits are read as 0. The write value should be 0.
0: ACK transmission
1: NACK transmission and reception of ACK/NACK
These bits are read as 0. The write value should be 0.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
IICCSC IICINT
M
0 0
2
C mode.
2
C mode.
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