Renesas RX100 Series User Manual page 250

RX13T Group
Table 16.2 Values of Bits CHNE, SQEND, and INDX in the Sequence Transfer and DTC Operation
CHNE Bit SQEND Bit
0 0
1 0
0 0
0 1
0 1
Note: Do not set the values other than listed above.
DTS Bit (DTC Transfer Mode Select)
The DTS bit specifies the side (transfer source or destination) to be a repeat area or block area in repeat transfer mode or
block transfer mode.
CHNS Bit (DTC Chain Transfer Select)
The CHNS bit selects the chain transfer condition.
When the CHNE bit is 0, setting of the CHNS bit is ignored. For details on the conditions to select the chain transfer,
refer to Table 16.4, Chain Transfer Conditions .
When the next transfer is chain transfer, completion of the specified number of transfers is not determined, the interrupt
status flag for the request source is not cleared, and an interrupt request to the CPU is not generated.
CHNE Bit (DTC Chain Transfer Enable)
The CHNE bit enables or disables chain transfer.
The chain transfer condition is selected by the CHNS bit.
For details of chain transfer, refer to section 16.4.6, Chain Transfer .
Refer to Table 16.2 for the setting value to be used in the sequence transfer.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
INDX Bit Operation
1 Start sequence transfer
0 Continue sequence transfer
0 Suspend sequence transfer
0 End sequence transfer
1 End current sequence transfer
and start new sequence transfer
16. Data Transfer Controller (DTCb)
Usage
Use this setting for the transfer information that is first
read in response to a transfer request from the source
specified in the DTCSQE register.
Use this setting for the first or intermediate transfer
information in a sequence.
Use this setting for the first or intermediate transfer
information in a sequence.
Use this setting with the last transfer information in a
sequence.
Use this setting with the last transfer information in a
sequence.
Page 250 of 1041