Overview; Outline Of Specifications - Renesas RX100 Series User Manual

RX13T Group
1.

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different
packages.
Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1 Outline of Specifications (1/3)
Classification Module/Function
CPU CPU
FPU
Memory ROM
RAM
E2 DataFlash
MCU operating mode
Clock Clock generation circuit
Resets
Voltage detection Voltage detection circuit
(LVDAb)
Low power Low power consumption
consumption functions
Function for lower operating
power consumption
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Description
 Maximum operating frequency: 32 MHz
 32-bit RX CPU
 Minimum instruction execution time: One instruction per clock cycle
 Address space: 4-Gbyte linear
 Register set
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit registers
 Basic instructions: 73 Variable-length instruction format
 DSP instructions: 9
 Addressing modes: 10
 Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
 On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit
 On-chip divider: 32-bit ÷ 32-bit → 32 bits
 Barrel shifter: 32 bits
 Single precision (32-bit) floating point
 Data types and floating-point exceptions in conformance with the IEEE754 standard
 Capacity: 64 K/128 Kbytes
 32 MHz, no-wait memory access
 Programming/erasing method:
Serial programming (asynchronous serial communication), self-programming
 Capacity: 12 Kbytes
 32 MHz, no-wait memory access
 Capacity: 4 Kbytes
 Number of erase/write cycles: 1,000,000 (typ)
Single-chip mode
 Main clock oscillator, low-speed and high-speed on-chip oscillator, PLL frequency synthesizer, and
IWDT-dedicated on-chip oscillator
 Oscillation stop detection: Available
 Clock frequency accuracy measurement circuit (CAC): Available
 Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLKB: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,
64)
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
 When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 3 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
 Module stop function
 Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
 Operating power control modes
High-speed operating mode and middle-speed operating mode
1. Overview
Page 32 of 1041