Bus Priority Control Register (Buspri) - Renesas RX100 Series User Manual

RX13T Group
15.3.5

Bus Priority Control Register (BUSPRI)

Address(es): 0008 1310h
b15 b14
— —
0 0
Value after reset:
Bit Symbol
b1, b0 BPRA[1:0]
b3, b2 BPRO[1:0]
b5, b4 BPIB[1:0]
b7, b6 BPGB[1:0]
b9, b8 —
b11, b10 BPFB[1:0]
b15 to b12 —
Note 1. These bits can be written to only once while the DTC is stopped. When they are written to more than one time, the operation is
not guaranteed.
BPRA[1:0] Bits (Memory Bus 1 (RAM) Priority Control)
These bits specify the priority order for memory bus 1 (RAM).
When the priority order is fixed, internal main bus 2 has priority over the CPU bus.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPRO[1:0] Bits (Memory Bus 2 (ROM) Priority Control)
These bits specify the priority order for memory bus 2 (ROM).
When the priority order is fixed, internal main bus 2 has priority over the CPU bus.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
BPIB[1:0] Bits (Internal Peripheral Bus 1 Priority Control)
These bits specify the priority order for internal peripheral bus 1.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1.
When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — BPFB[1:0]
0 0 0 0
Bit Name
Memory Bus 1 (RAM) Priority
Control
Memory Bus 2 (ROM) Priority
Control
Internal Peripheral Bus 1 Priority
Control
Internal Peripheral Buses 2 and
3 Priority Control
Reserved
Internal Peripheral Bus 6 Priority
Control
Reserved
b9 b8 b7 b6
— — BPGB[1:0]
0 0 0 0
Description
b1 b0
0 0: The order of priority is fixed.
0 1: The order of priority is toggled.
1 0: Setting prohibited
1 1: Setting prohibited
b3 b2
0 0: The order of priority is fixed.
0 1: The order of priority is toggled.
1 0: Setting prohibited
1 1: Setting prohibited
b5 b4
0 0: The order of priority is fixed.
0 1: The order of priority is toggled.
1 0: Setting prohibited
1 1: Setting prohibited
b7 b6
0 0: The order of priority is fixed.
0 1: The order of priority is toggled.
1 0: Setting prohibited
1 1: Setting prohibited
These bits are read as 0. The write value should be 0.
b11 b10
0 0: The order of priority is fixed.
0 1: The order of priority is toggled.
1 0: Setting prohibited
1 1: Setting prohibited
These bits are read as 0. The write value should be 0.
b5 b4 b3 b2
BPIB[1:0] BPRO[1:0]
0 0 0 0
Page 240 of 1041
15. Buses
b1 b0
BPRA[1:0]
0 0
R/W
R/(W)
1
*
R/(W)
* 1
R/(W)
1
*
R/(W)
1
*
R/W
R/(W)
1
*
R/W