Port Output Enable Control Register 4 (Poecr4) - Renesas RX100 Series User Manual

RX13T Group
20.2.10

Port Output Enable Control Register 4 (POECR4)

Address(es): POE.POECR4 0008 C4D0h
b15 b14
— —
Value after reset: 0 0
Bit Symbol
b0 CMADDMT34ZE
b1 —
b2 —
b3 IC3ADDMT34ZE
b4 IC4ADDMT34ZE
b9 to b5 —
b10 —
b15 to b11 —
Note 1. Can be modified only once after a reset.
The POECR4 register is used to extend the control conditions to put the output of the MTU complementary PWM output
pins (MTU3 and MTU4) in the high-impedance state.
CMADDMT34ZE Bit (MTU3 and MTU4 High-Impedance Condition CFLAG Add)
Adds the POECMPFR.CnFLAG flag (n = 0 to 2) to the high-impedance control conditions for the MTU3 and MTU4
pins (MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, MTIOC4D).
However, when the pins are in the high-impedance state by the flag, an OEIn interrupt (n = 1, 3, 4) will not be generated.
IC3ADDMT34ZE Bit (MTU3 and MTU4 High-Impedance Condition POE8F Add)
Adds the ICSR3.POE8F flag to the high-impedance control conditions for the MTU3 and MTU4 pins (MTIOC3B,
MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, MTIOC4D).
IC4ADDMT34ZE Bit (MTU3 and MTU4 High-Impedance Condition POE10F Add)
Adds the ICSR4.POE10F flag to the high-impedance control conditions for the MTU3 and MTU4 pins (MTIOC3B,
MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, MTIOC4D).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
— — — —
0 0 0 1
Bit Name
MTU3 and MTU4 High-
Impedance Condition CFLAG
Add
Reserved
Reserved
MTU3 and MTU4 High-
Impedance Condition POE8F
Add
MTU3 and MTU4 High-
Impedance Condition POE10F
Add
Reserved
Reserved
Reserved
b9 b8 b7 b6
— — — —
0 0 0 0
Description
0: Does not add the flags to the conditions to put the
output in the high-impedance state.
1: Adds the flags to the conditions to put the output in the
high-impedance state.
This bit is read as 1. The write value should be 1.
This bit is read as 0. The write value should be 0.
0: Does not add the flag to the conditions to put the
output in the high-impedance state.
1: Adds the flag to the conditions to put the output in the
high-impedance state.
0: Does not add the flag to the conditions to put the
output in the high-impedance state.
1: Adds the flag to the conditions to put the output in the
high-impedance state.
These bits are read as 0. The write value should be 0.
This bit is read as 1. The write value should be 1.
These bits are read as 0. The write value should be 0.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
IC4ADD IC3ADD
— —
MT34ZE MT34ZE
0 0 0 0
Page 541 of 1041
b1 b0
CMADD
—
MT34ZE
1 0
R/W
1
R/W*
R/W
R/W
R/W* 1
1
R/W*
R/W
R/W
R/W