Slave Transmit Operation - Renesas RX100 Series User Manual

RX13T Group
24.3.5

Slave Transmit Operation

In slave transmit operation, the master device outputs the SCL clock, the RIIC transmits data as a slave device, and the
master device returns acknowledgments.
Figure 24.15 shows an example of usage of slave transmission and Figure 24.16 and Figure 24.17 show the timing of
operations in slave transmission.
The following describes the procedure and operations for slave transmission.
(1) Initial settings. For details, refer to section 24.3.2, Initial Settings .
After initial settings, the RIIC will stay in the standby state until it receives a slave address that it matches.
(2) After receiving a matching slave address, the RIIC sets one of the corresponding bits ICSR1.HOA, GCA, and AASy
(y = 0 to 2) to 1 on the rising edge of the ninth cycle of SCL clock (the clock signal) and outputs the value set in the
ICMR3.ACKBT bit to the acknowledge bit on the ninth cycle of SCL clock. If the value of the R/W# bit that was
also received at this time is 1, the RIIC automatically places itself in slave transmit mode by setting both the
ICCR2.TRS bit and the ICSR2.TDRE flag to 1.
(3) After the ICSR2.TDRE flag is confirmed to be 1, write the data for transmission to the ICDRT register. At this time,
if the RIIC does not receive acknowledge from the master device (receives an NACK signal) while the
ICFER.NACKE bit is 1, the RIIC aborts transfer of the next data.
(4) Wait until the ICSR2.TEND flag is set to 1 while the ICSR2.TDRE flag is 1, after the ICSR2.NACKF flag is set to
1 or the last byte for transmission is written to the ICDRT register. When the ICSR2.NACKF flag or the TEND flag
is 1, the RIIC drives the SCL0 line low on the ninth falling edge of SCL clock.
(5) When the ICSR2.NACKF flag or the ICSR2.TEND flag is 1, dummy read the ICDRR register to complete the
processing. This releases the SCL0 line.
(6) Upon detecting the stop condition, the RIIC automatically sets bits ICSR1.HOA, GCA, and AASy (y = 0 to 2), flags
ICSR2.TDRE and TEND, and the ICCR2.TRS bit to 0, and enters slave receive mode.
(7) After checking that the ICSR2.STOP flag is 1, set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
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24. I C-bus Interface (RIICa)
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