Refresh Operation - Renesas RX100 Series User Manual

RX13T Group
22.3.3

Refresh Operation

The counter is refreshed and starts operation (counting is started by refreshing) by writing the values 00h and then FFh to
the IWDTRR register. If a value other than FFh is written after 00h, the counter is not refreshed. After such invalid
writing, correct refreshing is performed by again writing 00h and then FFh to the IWDTRR register.
When writing is done in the order of 00h (first time) → 00h (second time), and if FFh is written after that, the writing
order 00h → FFh is satisfied; writing 00h (n–1-th time) → 00h (nth time) → FFh is valid and correct refreshing will be
done. Even when the first value written before 00h is not 00h, correct refreshing will be done if the operation contains the
set of writing 00h → FFh. Moreover, even if a register other than the IWDTRR register is accessed or the IWDTRR
register is read between writing 00h and writing FFh to the IWDTRR register, correct refreshing will be done.
[Sample sequences of writing that are valid for refreshing the counter]
 00h → FFh
 00h (n–1-th time) → 00h (nth time) → FFh
 00h → access to another register or read from the IWDTRR register → FFh
[Sample sequences of writing that are not valid for refreshing the counter]
 23h (a value other than 00h) → FFh
 00h → 54h (a value other than FFh)
 00h → AAh (00h and a value other than FFh) → FFh
Even when 00h is written to the IWDTRR register outside the refresh-permitted period, if FFh is written to the IWDTRR
register in the refresh-permitted period, the writing sequence is valid and refreshing will be done.
After FFh is written to the IWDTRR register, refreshing the counter requires up to four cycles of the signal for counting
(the IWDTCR.CKS[3:0] bits determine how many cycles of the IWDT-dedicated clock (IWDTCLK) make up one cycle
for counting). Therefore, writing FFh to the IWDTRR register should be completed four-count cycles before the end
position of the refresh-permitted period or a counter underflow. The value of the counter can be checked by the
IWDTSR.CNTVAL[13:0] bits.
[Sample refreshing timings]
 When the window start position is set to 03FFh, even if 00h is written to the IWDTRR register before 03FFh is
reached (0402h, for example), refreshing is done if FFh is written to the IWDTRR register after the value of the
IWDTSR.CNTVAL[13:0] bits has reached 03FFh.
 When the window end position is set to 03FFh, refreshing is done if 0403h (four-count cycles before 03FFh) or a
greater value is read from the IWDTSR.CNTVAL[13:0] bits immediately after writing 00h → FFh to the IWDTRR
register.
 When the refresh-permitted period continues until count 0000h, refreshing can be done immediately before an
underflow. In this case, if 0003h (four-count cycles before an underflow) or a greater value is read from the
IWDTSR.CNTVAL[13:0] bits immediately after writing 00h → FFh to the IWDTRR register, no underflow occurs
and refreshing is done.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
22. Independent Watchdog Timer (IWDTa)
Page 577 of 1041