Timer Waveform Control Register (Twcra) - Renesas RX100 Series User Manual

RX13T Group
19.2.31

Timer Waveform Control Register (TWCRA)

Address(es): MTU.TWCRA 0009 5260h
b7 b6
CCE —
*1
Value after reset: 0 0
Bit Symbol Bit Name
b0 WRE Waveform Retain Enable
b6 to b1 — Reserved
b7 CCE Compare Match Clear Enable
*1
Note 1. Do not set to 1 when complementary PWM mode 1 is not selected.
TWCRA controls the output waveform when synchronous counter clearing occurs in MTU3.TCNT and MTU4.TCNT in
complementary PWM mode and specifies whether to clear the counters at MTU3.TGRA compare match.
The CCE bit and WRE bit in TWCRA should be modified only while TCNT stops.
WRE Bit (Waveform Retain Enable)
This bit selects the waveform output when synchronous counter clearing occurs in complementary PWM mode.
The initial output is inhibited with this function only when synchronous clearing occurs within the Tb interval at the
trough in complementary PWM mode. When synchronous clearing occurs outside this interval, the initial values
specified in TOCR1A and TOCR2A are output regardless of the WRE bit setting. The initial values specified in
TOCR1A and TOCR2A are also output when synchronous clearing occurs in the Tb interval at the trough immediately
after MTU3.TCNT and MTU4.TCNT start operation.
For the Tb interval at the trough in complementary PWM mode, refer to Figure 19.47 .
[Setting condition]
 When 1 is written to the WRE bit after reading WRE = 0
CCE Bit (Compare Match Clear Enable)
This bit specifies whether to clear counters at MTU3.TGRA compare match in complementary PWM mode.
[Setting condition]
 When 1 is written to CCE after reading CCE = 0
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Description
0: Initial values specified in TOCR1A and TOCR2A are output
1: Initial output is inhibited
These bits are read as 0. The write value should be 0.
0: Counters are not cleared at MTU3.TGRA compare match
1: Counters are cleared at MTU3.TGRA compare match
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
— WRE
0 0
R/W
R/(W)
R/W
R/(W)
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