Renesas RX100 Series User Manual page 114

RX13T Group
Voltage detection 1 circuit
LVD1LVL[3:0]
VCC
LVD1E
Level
selection
circuit
+
(9 levels)
-
Internal reference
voltage
(for detection of Vdet1)
Voltage detection 1 signal will be high
when the LVD1E bit is 0 (disabled)
LVD1E: Bit in LVCMPCR
LVD1LVL[3:0]: Bits in LVDLVLR
LVD1CMPE, LVD1RIE, LVD1RI, LVD1RN: Bits in LVD1CR0
LVD1IDTSEL[1:0], LVD1IRQSEL: Bits in LVD1CR1
LVD1DET: Bit in LVD1SR
Figure 8.2 Block Diagram of Voltage Monitoring 1 Interrupt/Reset Circuit
Voltage detection 2 circuit
VCC
LVD2LVL[1:0]
LVD2E
Level
selection
circuit
(4 levels)
Internal reference
voltage
(for detection of Vdet2)
Voltage detection 2 signal will be high
when the LVD2E bit is 0 (disabled)
LVD2E: Bits in LVCMPCR
LVD2LVL[1:0]: Bits in LVDLVLR
LVD2CMPE, LVD2RIE, LVD2RI, LVD2RN: Bits in LVD2CR0
LVD2IDTSEL[1:0], LVD2IRQSEL: Bits in LVD2CR1
LVD2DET: Bit in LVD2SR
Figure 8.3 Block Diagram of Voltage Monitoring 2 Interrupt/Reset Circuit
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
LVD1CMPE
Analog
noise filter
Voltage detection 1
signal
LVD2CMPE
Analog
+
noise filter Voltage
detection 2
-
signal
8. Voltage Detection Circuit (LVDAb)
Voltage monitoring 1 interrupt/reset circuit
The setting of the LVD1DET bit will be 0
LVD1SR register
if 0 (undetected) is written in the program.
b1
LVD1RIE
LVD1MON bit
LVD1RI
LVD1RN = 0
Fixed
period
negation LVD1RN = 1
LVD1DET
Edge
selection
circuit
LVD1IDTSEL[1:0]
LVD1IRQSEL
Voltage monitoring 2 interrupt/reset circuit
The setting of the LVD2DET bit will be 0
LVD2SR register if 0 (undetected) is written by the program.
b1
LVD2RIE
LVD2MON bit LVD2RI
LVD2RN = 0
Fixed
period
negation LVD2RN = 1
LVD2DET
Edge
selection
circuit
LVD2IDTSEL[1:0]
LVD2IRQSEL
Voltage monitoring 1
reset signal
(low is valid)
Voltage monitoring 1
non-maskable
interrupt signal
Voltage monitoring 1
maskable interrupt
signal
Voltage
monitoring 2
reset signal
(low is valid)
Voltage
monitoring 2
non-maskable
interrupt signal
Voltage
monitoring 2
maskable
interrupt signal
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