Renesas RX100 Series User Manual page 771

RX13T Group
S 1 2
SCL0
SDA0
b7 b6
7-bit slave address
BBSY
MST
TRS
TDRE
Receive data (7-bit address + W)
TEND
RDRF
AASy
ICDRT
ICDRS
XXXX (Initial value/last data for reception)
ICDRR
ACKBT
X (ACK/NACK)
ACKBR
START
NACKF
Figure 24.19 Slave Receive Operation Timing (1) (7-Bit Address Format, when RDRFS bit is 0)
7 8 9
SCL0
SDA0
ACK
b1 b0 b7
DATA n-2
BBSY
MST
TRS
TDRE
Receive data (DATA n-2)
TEND
RDRF
AASy
ICDRT
ICDRS DATA n-2
ICDRR DATA n-3
ACKBT
ACKBR
STOP
NACKF
Read ICDRR
register
(DATA n-2)
[3] [4]
Figure 24.20 Slave Receive Operation Timing (2) (when RDRFS bit is 0)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
3 4 5 6 7 8
b5 b4 b3 b2 b1 b0
W
XXXX (Initial value/last data for transmission)
7-bit address + W
1 2 3 4 5 6
b6 b5 b4 b3 b2
DATA n-1
Receive data (DATA n-1)
XXXX (Initial value/last data for transmission)
DATA n-1
DATA n-2
0 (ACK)
(to prevent failure to receive data)
9 1 2 3 4 5
ACK
b7 b6 b5 b4 b3
DATA 1
Receive data (DATA 1)
7-bit address + W
0 (ACK)
0 (ACK)
7 8 9 1 2 3
ACK
b1 b0 b7 b6 b5
0 (ACK)
0 (ACK)
Read ICDRR
register
(DATA n-1)
[3] [4]
2
24. I C-bus Interface (RIICa)
Automatic low hold
6 7 8 9 1
ACK
b2 b1 b0 b7
DATA 1
Read ICDRR register
(Dummy read
[7-bit address + W])
[3]
4 5 6 7 8 9
ACK
b4 b3 b2 b1 b0
DATA n
Receive data (DATA n)
DATA n
DATA n-1
Read ICDRR
2 3 4
b6 b5 b4
DATA 2
DATA 2
DATA 1
0 (ACK)
Read ICDRR
register
(DATA 1)
[3][4]
P
DATA n
0 (ACK)
Clear
register
STOP flag
(DATA n)
[3] [4] [6]
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