Renesas R5F513T3ADFJ Manuals

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Renesas R5F513T3ADFJ User Manual (1041 pages)

32-Bit MCU

Brand: Renesas | Category: Microcontrollers | Size: 14.13 MB

Table of Contents
7
Features

31
Overview

32
- Outline of Specifications
  32
- List of Products
  36
- Block Diagram
  37
- Pin Functions
  38
- Pin Assignments
  40
Cpu

44
Operating Modes

74
Address Space

79
I/O Registers

81
- I/O Register Addresses (Address Order)
  83
Resets

94
- Overview
  94
- Register Descriptions
  96
- Operation
  100
Option-Setting Memory (OFSM)

106
- Overview
  106
- Register Descriptions
  107
- Usage Note
  111
  - Setting Example of Option-Setting Memory
    111
Voltage Detection Circuit (Lvdab)

112
Clock Generation Circuit

129
Clock Frequency Accuracy Measurement Circuit (CAC)

156
- Overview
  156
- Register Descriptions
  158
- Operation
  164
  - Measuring Clock Frequency
    164
  - Digital Filtering of Signals on the CACREF Pin
    165
- Interrupt Requests
  165
- Usage Notes
  166
  - Module Stop Function Setting
    166
Low Power Consumption

167
- Overview
  167
- Register Descriptions
  171
- Reducing Power Consumption by Switching Clock Signals
  177
- Module Stop Function
  177
- Function for Lower Operating Power Consumption
  178
  - Setting Operating Power Control Mode
    178
- Low Power Consumption Modes
  179
  - Sleep Mode
    179
    
    Entry to Sleep Mode
    179
    
    Exit from Sleep Mode
    180
  - Deep Sleep Mode
    181
    
    Entry to Deep Sleep Mode
    181
    
    Exit from Deep Sleep Mode
    182
  - Software Standby Mode
    183
    
    Entry to Software Standby Mode
    183
    
    Exit from Software Standby Mode
    184
    
    Example of Software Standby Mode Application
    185
- Usage Notes
  186
  - I/O Port States
    186
  - Module Stop State of DTC
    186
  - On-Chip Peripheral Module Interrupts
    186
  - Write Access to MSTPCRA, MSTPCRB, and MSTPCRC
    186
  - Timing of WAIT Instructions
    186
  - Rewrite the Register by DTC in Sleep Mode
    186
Register Write Protection Function

187
- Register Descriptions
  188
  - Protect Register (PRCR)
    188
Exception Handling

189
- Exception Events
  189
  - Undefined Instruction Exception
    190
  - Privileged Instruction Exception
    190
  - Floating-Point Exception
    190
  - Reset
    190
  - Non-Maskable Interrupt
    190
  - Interrupts
    190
  - Unconditional Trap
    190
- Exception Handling Procedure
  191
- Acceptance of Exception Events
  193
  - Acceptance Timing and Saved PC Value
    193
  - Vector and Site for Saving the Values in the PC and PSW
    193
- Hardware Processing for Accepting and Returning from Exceptions
  194
- Hardware Pre-Processing
  195
  - Undefined Instruction Exception
    195
  - Privileged Instruction Exception
    195
  - Floating-Point Exception
    195
  - Reset
    195
  - Non-Maskable Interrupt
    195
  - Interrupt
    196
  - Unconditional Trap
    196
- Return from Exception Handling Routine
  197
- Priority of Exception Events
  197
Interrupt Controller (Icub)

198
Buses

232
- Overview
  232
- Description of Buses
  234
  - CPU Buses
    234
  - Memory Buses
    234
  - Internal Main Buses
    234
  - Internal Peripheral Buses
    235
  - Write Buffer Function (Internal Peripheral Bus)
    236
  - Parallel Operation
    237
  - Restrictions
    237
- Register Descriptions
  238
- Bus Error Monitoring Section
  242
  - Type of Bus Error
    242
    
    Illegal Address Access
    242
    
    Timeout
    242
  - Operations When a Bus Error Occurs
    242
  - Conditions Leading to Bus Errors
    243
- Interrupt
  244
  - Interrupt Source
    244
Data Transfer Controller (Dtcb)

245
- Overview
  245
- Register Descriptions
  247
- Request Sources
  261
  - Allocating Transfer Information and DTC Vector Table
    261
- Operation
  263
  - Transfer Information Read Skip Function
    265
  - Transfer Information Write-Back Skip Function
    266
    
    Write-Back Skip by Fixing Addresses
    266
    
    Write-Back Skip by the MRA.WBDIS Bit
    266
  - Normal Transfer Mode
    267
  - Repeat Transfer Mode
    268
  - Block Transfer Mode
    269
  - Chain Transfer
    270
  - Operation Timing
    271
  - Execution Cycles of the DTC
    274
  - DTC Bus Mastership Release Timing
    274
  - Sequence Transfer
    275
  - DTC Index Table
    277
  - Example of Sequence Transfer
    279
- DTC Setting Procedure
  285
- Examples of DTC Usage
  286
  - Normal Transfer
    286
  - Chain Transfer When the Counter Is 0
    287
  - Sequence Transfer
    288
- Interrupt Source
  289
- Low Power Consumption Function
  290
- Usage Notes
  291
I/O Ports

293
- Overview
  293
- I/O Port Configuration
  295
- Register Descriptions
  297
  - Port Direction Register (PDR)
    297
  - Port Output Data Register (PODR)
    298
  - Port Input Data Register (PIDR)
    299
  - Port Mode Register (PMR)
    300
  - Open Drain Control Register 0 (ODR0)
    301
  - Open Drain Control Register 1 (ODR1)
    302
  - Pull-Up Control Register (PCR)
    303
  - Drive Capacity Control Register (DSCR)
    304
- Initialization of the Port Direction Register (PDR)
  305
- Handling of Unused Pins
  306
Multi-Function Pin Controller (MPC)

307
Multi-Function Timer Pulse Unit 3 (Mtu3C)

322
Port Output Enable 3 (POE3C)

527
Compare Match Timer (CMT)

557
- Overview
  557
- Register Descriptions
  558
- Operation
  560
  - Periodic Count Operation
    560
  - CMCNT Count Timing
    560
- Interrupts
  561
  - Interrupt Sources
    561
  - Timing of Compare Match Interrupt Generation
    561
- Usage Notes
  562
Independent Watchdog Timer (Iwdta)

563
- Overview
  563
- Register Descriptions
  565
- Operation
  572
  - Count Operation in each Start Mode
    572
    
    Register Start Mode
    572
    
    Auto-Start Mode
    574
    
    Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers
    576
  - Refresh Operation
    577
  - Status Flags
    579
  - Reset Output
    579
  - Interrupt Sources
    579
  - Reading the Counter Value
    580
  - Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers
    581
- Usage Notes
  581
  - Refresh Operations
    581
  - Clock Divide Ratio Setting
    581
Serial Communications Interface (Scig, Scih)

582
I 2 C-Bus Interface (Riica)

724
- Overview
  724
- Register Descriptions
  727
- Operation
  756
  - Communication Data Format
    756
  - Initial Settings
    757
  - Master Transmit Operation
    758
  - Master Receive Operation
    761
  - Slave Transmit Operation
    767
  - Slave Receive Operation
    770
- SCL Synchronization Circuit
  772
- SDA Output Delay Function
  773
- Digital Noise Filter Circuit
  774
- Address Match Detection
  775
  - Slave-Address Match Detection
    775
  - Detection of the General Call Address
    777
  - Device-ID Address Detection
    778
  - Host Address Detection
    780
- Automatic Low-Hold Function for SCL
  781
- Arbitration-Lost Detection Functions
  785
- 24.10 Start Condition/Restart Condition/Stop Condition Issuing Function
  789
  - Issuing a Start Condition
    789
  - Issuing a Restart Condition
    789
  - Issuing a Stop Condition
    790
- 24.11 Bus Hanging
  791
  - Timeout Function
    791
  - Extra SCL Clock Cycle Output Function
    793
  - RIIC Reset and Internal Reset
    794
- 24.12 Smbus Operation
  795
- 24.13 Interrupt Sources
  797
  - Buffer Operation for TXI and RXI Interrupts
    797
- Initialization of Registers and Functions When a Reset Is Issued or a Condition Is Detected
  798
- 24.15 Usage Notes
  799
  - Setting Module Stop Function
    799
  - Notes on Starting Transfer
    799
CRC Calculator (CRC)

800
- Overview
  800
- Register Descriptions
  801
- Operation
  803
- Usage Notes
  806
  - Module Stop Function Setting
    806
  - Note on Transmission
    806
26 12-Bit A/D Converter (S12ADF)

807
D/A Converter for Generating Comparator C Reference Voltage (DA)

883
- Overview
  883
- Register Descriptions
  884
- Operation
  886
- Usage Notes
  887
Comparator C (CMPC)

888
- Overview
  888
- Register Descriptions
  891
- Operation
  895
  - Comparator Operation Example
    895
  - Noise Filter
    896
  - Interrupts
    897
  - Comparator Pin Output
    897
  - Comparator Setting Flowchart
    898
- Usage Notes
  899
Data Operation Circuit (DOC)

900
- Overview
  900
- Register Descriptions
  901
- Operation
  903
  - Data Comparison Mode
    903
  - Data Addition Mode
    904
  - Data Subtraction Mode
    905
- Interrupt Requests
  905
- Usage Note
  905
  - Module Stop Function Setting
    905
Ram

906
- Overview
  906
- Operation
  906
  - Low Power Consumption Function
    906
Flash Memory (FLASH)

907
- Overview
  907
- ROM Area and Block Configuration
  908
- E2 Dataflash Area and Block Configuration
  909
- Register Descriptions
  910
- Start-Up Program Protection
  930
- Area Protection
  931
- Programming and Erasure
  932
  - Sequencer Modes
    932
    
    E2 Dataflash Access Disabled Mode
    932
    
    Read Mode
    933
    
    P/E Modes
    933
  - Mode Transitions
    933
    
    Transition from E2 Dataflash Access Disable Mode to Read Mode
    933
    
    Transition from Read Mode to P/E Mode
    934
    
    Transition from P/E Mode to Read Mode
    936
  - Software Commands
    938
  - Software Command Usage
    939
    
    Program
    939
    
    Block Erase
    941
    
    Blank Check
    943
    
    Start-Up Area Information Program/Access Window Information Program
    945
    
    Unique ID Read
    946
    
    Forced Stop of Software Commands
    947
  - Interrupt
    947
- Boot Mode
  948
  - Boot Mode (SCI Interface)
    949
    
    Operating Conditions in Boot Mode (SCI Interface)
    949
    
    Starting up in Boot Mode (SCI Interface)
    950
  - Boot Mode (FINE Interface)
    951
    
    Operating Conditions in Boot Mode (FINE Interface)
    951
- Flash Memory Protection
  952
  - ID Code Protection
    952
    
    Boot Mode ID Code Protection
    953
    
    On-Chip Debugging Emulator ID Code Protection
    954
- 31.10 Communication Protocol
  955
  - State Transition in Boot Mode (SCI Interface)
    955
  - Command and Response Configuration
    956
  - Response to Undefined Commands
    956
  - Boot Mode Status Inquiry
    957
  - Inquiry Commands
    958
    
    Supported Device Inquiry
    958
    
    Data Area Availability Inquiry
    959
    
    User Area Information Inquiry
    959
    
    Data Area Information Inquiry
    960
    
    Block Information Inquiry
    960
  - Setting Commands
    961
    
    Device Select
    961
    
    Operating Frequency Select
    962
    
    Program/Erase Host Command Wait State Transition
    963
  - ID Code Authentication Command
    964
    
    ID Code Check
    964
  - Program/Erase Commands
    965
    
    User/Data Area Program Preparation
    965
    
    Program
    966
    
    Data Area Program
    967
    
    Erase Preparation
    968
    
    Block Erase
    968
  - Read-Check Commands
    969
    
    Memory Read
    969
    
    User Area Checksum
    970
    
    Data Area Checksum
    971
    
    User Area Blank Check
    971
    
    Data Area Blank Check
    972
    
    Access Window Information Program
    972
    
    Access Window Read
    973
- Serial Programmer Operation in Boot Mode (SCI Interface)
  974
- 31.12 Rewriting by Self-Programming
  985
  - Overview
    985
- 31.13 Usage Notes
  986
- 31.14 Usage Notes in Boot Mode
  987
Electrical Characteristics

988
- Absolute Maximum Ratings
  988
- Recommended Operating Conditions
  988
- DC Characteristics
  989
  - Normal I/O Pin Output Voltage Characteristics
    996
- AC Characteristics
  998
  - Clock Timing
    998
  - Reset Timing
    1002
  - Timing of Recovery from Low Power Consumption Modes
    1003
  - Control Signal Timing
    1005
  - Timing of On-Chip Peripheral Modules
    1006
- A/D Conversion Characteristics
  1017
- Programmable Gain Amplifier Characteristics
  1021
- Comparator Characteristics
  1022
- D/A Conversion Characteristics
  1023
- Power-On Reset Circuit and Voltage Detection Circuit Characteristics
  1024
- 32.10 Oscillation Stop Detection Timing
  1028
- 32.11 ROM (Code Flash Memory) Characteristics
  1029
- 32.12 E2 Dataflash (Data Flash Memory) Characteristics
  1031
- 32.13 Usage Notes
  1032
  - Connecting VCL Capacitor and Bypass Capacitors
    1032
Appendix 1. Port States in each Processing Mode

1035
Appendix 2. Package Dimensions

1036
Revision History

1038

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Renesas R5F513T3ADFJ Manuals

Renesas R5F513T3ADFJ User Manual (1041 pages)

Table of Contents

Features

Overview

Cpu

Operating Modes

Address Space

I/O Registers

Resets

Option-Setting Memory (OFSM)

Voltage Detection Circuit (Lvdab)

Clock Generation Circuit

Clock Frequency Accuracy Measurement Circuit (CAC)

Low Power Consumption

Register Write Protection Function

Exception Handling

Interrupt Controller (Icub)

Buses

Data Transfer Controller (Dtcb)

I/O Ports

Multi-Function Pin Controller (MPC)

Multi-Function Timer Pulse Unit 3 (Mtu3C)

Port Output Enable 3 (POE3C)

Compare Match Timer (CMT)

Independent Watchdog Timer (Iwdta)

Serial Communications Interface (Scig, Scih)

I 2 C-Bus Interface (Riica)

CRC Calculator (CRC)

26 12-Bit A/D Converter (S12ADF)

D/A Converter for Generating Comparator C Reference Voltage (DA)

Comparator C (CMPC)

Data Operation Circuit (DOC)

Ram

Flash Memory (FLASH)

Electrical Characteristics

Appendix 1. Port States in each Processing Mode

Appendix 2. Package Dimensions

Revision History

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