Multi-Processor Serial Data Reception - Renesas RX100 Series User Manual

RX13T Group
23.4.2

Multi-Processor Serial Data Reception

Figure 23.20 and Figure 23.21 are sample flowcharts of multi-processor data reception. When the SCR.MPIE bit is set
to 1, reading the communication data is skipped until reception of the communication data in which the multi-processor
bit is set to 1. When the communication data in which the multi-processor bit is set to 1 is received, the received data is
transferred to RDR (the RDRH and RDRL registers when 9-bit data length is selected). During this time, the RXI
interrupt request is generated. The other operations are the same as the operations in asynchronous mode.
Figure 23.19 is the example of operation for reception.
Start bit
0
MPIE
RXI interrupt flag
*1
(IRn In ICU )
RDR value
Start bit
0
MPIE
RXI interrupt flag
*1
(IRn In ICU )
RDR value
Note 1. Refer to section 14, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
Figure 23.19 Example of SCI Reception (8-Bit Data/Multi-Processor Bit/1 Stop Bit)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Data (ID1)
MPB
D0 D1 D7 1
MPIE = 0
RXI interrupt request
(multi-processor
interrupt) generated
(a) When the received ID does not match the ID of the receiving station itself
Data (ID2)
MPB
D0 D1 D7 1
ID1
RXI interrupt request
MPIE = 0
(multi-processor
interrupt) generated
(b) When the received ID matches the ID of the receiving station itself
23. Serial Communications Interface (SCIg, SCIh)
Data (Data1)
Stop bit Start bit
1 0 D0 D1
RDR data read in RXI
MPIE bit set to 1 again
interrupt handling
when the received ID
routine
does not match the ID of
the receiving station itself
Data (Data2)
Stop bit Start bit
1 0 D0 D1
ID2
Since the received ID matches
RDR data read in RXI
the ID of the receiving station
interrupt handling
itself, reception continued and
routine
data received in RXI interrupt
handling routine
Stop bit
MPB
D7 0 1
Idle state
(mark state)
ID1
RXI interrupt request not
generated. RDR retains
the state.
MPB Stop bit
D7 0 1 Idle state
(mark state)
Data2
MPIE bit set to 1 again
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