Timer Read/Write Enable Register (Trwera) - Renesas RX100 Series User Manual

32-bit mcu
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19.2.19

Timer Read/Write Enable Register (TRWERA)

Address(es): MTU.TRWERA 0009 5284h
b7
b6
Value after reset:
0
0
Bit
Symbol
Bit Name
b0
RWE
Read/Write Enable
b7 to b1
Reserved
TRWERA enables or disables access to the registers and counters that have write-protection capability against accidental
modification in MTU3 and MTU4.
RWE Bit (Read/Write Enable)
This bit enables or disables access to the registers that have write-protection capability against accidental modification.
[Clearing condition]
 When 0 is written to the RWE bit after reading RWE = 1
 Registers and Counters having Write-Protection Capability against Accidental Modification (TRWERA)
24 registers: MTUn.TCR, MTUn.TCR2, MTUn.TMDR1, MTUn.TIORH, MTUn.TIORL, MTUn.TIER, MTUn.TGRA,
MTUn.TGRB, MTU.TOERA, MTU.TOCR1A, MTU.TOCR2A, MTU.TGCRA, MTU.TCDRA, MTU.TDDRA, and
MTUn.TCNT (n = 3, 4)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5
b4
b3
b2
0
0
0
0
Description
0: Read/write access to the registers is disabled
1: Read/write access to the registers is enabled
These bits are read as 0. The write value should be 0.
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1
b0
RWE
0
1
R/W
R/W
R/W
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