Contention Between Mtu2.Tcnt Write Operation And Overflow/Underflow In Cascaded Operation - Renesas RX100 Series User Manual

RX13T Group
19.6.12 Contention between MTU2.TCNT Write Operation and Overflow/Underflow in
Cascaded Operation
With timer counters MTU1.TCNT and MTU2.TCNT in a cascade, when a contention occurs between MTU1.TCNT
counting (an MTU2.TCNT overflow/underflow) and the MTU2.TCNT write operation, the MTU2.TCNT write
operation is performed and the MTU1.TCNT count signal is disabled. In this case, if MTU1.TGRA works as a compare
match register and there is a match between the MTU1.TGRA and MTU1.TCNT values, a compare match signal is
issued.
Furthermore, when the MTU1.TCNT count clock is selected as the input capture source of MTU0, MTU0.TGRA to
MTU0.TGRD work in input capture mode. In addition, when the MTU0.TGRC compare match/input capture is selected
as the input capture source of MTU1.TGRB, MTU1.TGRB works in input capture mode.
Figure 19.132 shows the timing in this case.
When setting the TCNT clearing function in cascaded operation, be sure to synchronize MTU1 and MTU2.
MTU2.TGRA to MTU2.TGRB
MTU2 compare match signals A and B
MTU1.TCNT count clock
MTU1 compare match signal A
MTU1 input capture signal B
MTU0.TGRA to MTU0.TGRD
MTU0 input capture signals A to D
Figure 19.132

Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation

R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
PCLKB
MTU2.TCNT
MTU1.TCNT
MTU1.TGRA
MTU1.TGRB
MTU0.TCNT
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
Written by CPU
FFFEh FFFFh
MTU2.TCNT write data
FFFFh
M
M
N
P
Q
N N+1
Disabled
M
P
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