Low Power Consumption Function - Renesas RX100 Series User Manual

RX13T Group
16.8

Low Power Consumption Function

Before making a transition to the module stop state, deep sleep mode, or software standby mode, set the DTCST.DTCST
bit to 0 (DTC module stop), and then perform the following.
(1) Module Stop Function
Writing 1 (transition to the module-stop state is made) to the MSTPCRA.MSTPA28 bit enables the module stop function
of the DTC. If data transfer is in progress at the time 1 is written to the MSTPCRA.MSTPA28 bit, the transition to the
module stop state proceeds after data transfer has ended. While the MSTPCRA.MSTPA28 bit is 1, accessing the DTC
registers is prohibited.
Writing 0 (release from the module-stop state) to the MSTPCRA.MSTPA28 bit releases the DTC from the module stop
state.
(2) Deep Sleep Mode
Make settings according to the procedure under section 11.6.2.1, Entry to Deep Sleep Mode , in section 11, Low
Power Consumption .
If any data transfer is in progress at the time the WAIT instruction is executed, the transition to deep sleep mode follows
the completion of the data transfer.
The DTC is released from the module stop state by writing 0 to the MSTPCRA.MSTPA28 bit following recovery from
deep sleep mode.
(3) Software Standby Mode
Make settings according to the procedure under section 11.6.3.1, Entry to Software Standby Mode , in section 11,
Low Power Consumption .
If any data transfer is in progress at the time the WAIT instruction is executed, the transition to software standby mode
follows the completion of the data transfer.
(4) Notes on Low Power Consumption Function
For the WAIT instruction and the register setting procedure, refer to section 11.7.5, Timing of WAIT Instructions in
section 11, Low Power Consumption .
To perform data transfer after returning from a low power consumption mode, set the DTCST.DTCST bit to 1 again.
To use a request that is generated in deep sleep mode or software standby mode as an interrupt request to the CPU but not
as a DTC transfer request, specify the CPU as the interrupt request destination according to the description in section
14.4.3, Selecting Interrupt Request Destinations in section 14, Interrupt Controller (ICUb) , and then execute the
WAIT instruction.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
16. Data Transfer Controller (DTCb)
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