Noise Filter Setting Register (Snfr) - Renesas RX100 Series User Manual

RX13T Group
23.2.14

Noise Filter Setting Register (SNFR)

Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI12.SNFR 0008 B308h
b7 b6
— —
Value after reset: 0 0
Bit Symbol
b2 to b0 NFCS[2:0]
b7 to b3 —
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR are 0 (serial reception and transmission disabled).
NFCS[2:0] Bits (Noise Filter Clock Select)
These bits select the sampling clock for the digital noise filter. To use the noise filter in asynchronous mode, set these bits
2
to 000b. In simple I C mode, set the bits to a value in the range from 001b to 100b.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — —
0 0 0 0
Bit Name Description
Noise Filter Clock Select In asynchronous mode, the standard setting for the base clock is as
follows.
In simple I
on-chip baud rate generator selected by the SMR.CKS[1:0] bits are
given below.
Settings other than above are prohibited.
Reserved These bits are read as 0. The write value should be 0.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
NFCS[2:0]
0 0
b2 b0
0 0 0: The clock signal divided by 1 is used with the noise filter.
2
C mode, the standard settings for the clock source of the
b2 b0
0 0 1: The clock signal divided by 1 is used with the noise filter.
0 1 0: The clock signal divided by 2 is used with the noise filter.
0 1 1: The clock signal divided by 4 is used with the noise filter.
1 0 0: The clock signal divided by 8 is used with the noise filter.
R/W
R/W* 1
R/W
Page 618 of 1041