I 2 C-Bus Bit Rate Low-Level Register (Icbrl) - Renesas RX100 Series User Manual

RX13T Group
2
24.2.13 I C-bus Bit Rate Low-Level Register (ICBRL)
Address(es): RIIC0.ICBRL 0008 8310h
b7 b6
— —
1 1
Value after reset:
Bit Symbol Bit Name
b4 to b0 BRL[4:0] Bit Rate Low-Level Period
b7 to b5 — Reserved
ICBRL is a 5-bit register to set the low-level period of SCL clock.
It also works to generate the data setup time for automatic SCL low-hold operation (refer to section 24.8, Automatic
Low-Hold Function for SCL ); when the RIIC is used only in slave mode, this register needs to be set to a value longer
than the data setup time *
ICBRL counts the low-level period with the internal reference clock (IICφ) specified by the ICMR1.CKS[2:0] bits.
If the digital noise filter is enabled (the ICFER.NFE bit is 1), set the ICBRL register to a value at least one greater than
the number of stages in the noise filter. Regarding the number of stages in the noise filter, see the description of the
ICMR3.NF[1:0] bits.
Note 1. Data setup time (tSU: DAT)
250 ns (up to 100 kbps: Standard-mode (Sm))
100 ns (up to 400 kbps: Fast-mode (Fm))
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— BRL[4:0]
1 1 1 1
Description
Low-level period of SCL clock
These bits are read as 1. The write value should be 1.
1
.
b1 b0
1 1
2
24. I C-bus Interface (RIICa)
R/W
R/W
R/W
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