Parallel Operation; Restrictions - Renesas RX100 Series User Manual

RX13T Group
15.2.6

Parallel Operation

Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For
example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DTC is able to handle transfer
between a peripheral bus and peripheral bus at the same time.
An example of parallel operations is shown in Figure 15.4 . In this example, the CPU is able to employ the instruction
and operand buses for simultaneous access to ROM and RAM, respectively. Furthermore, the DTC simultaneously
employs internal main bus 2 for access to a peripheral bus during access to RAM and ROM by the CPU.
CPU instruction
CPU operand
Figure 15.4 Example of Parallel Operations
15.2.7

Restrictions

(1) Prohibition of Access that Spans Multiple Areas of Address Space
Single access that spans two areas of the address space is prohibited, and operation of such an access is not guaranteed.
Ensure that a single word or longword access does not span across two areas by crossing address space area boundaries.
(2) Restrictions on RMPA and String-Manipulation Instructions
(a) The allocation of data to be handled by RMPA or string-manipulation instructions to I/O registers is prohibited,
and operation is not guaranteed if this restriction is not observed.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
ROM
fetching
RAM
Peripheral bus access
Peripheral bus
DTC
ROM access
ROM ROM ROM ROM
RAM access
RAM RAM RAM RAM
Peripheral bus access
Peripheral bus
ROM ROM
RAM RAM
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15. Buses