Register Descriptions; System Clock Control Register (Sckcr) - Renesas RX100 Series User Manual

RX13T Group
9.2

Register Descriptions

9.2.1

System Clock Control Register (SCKCR)

Address(es): 0008 0020h
b31 b30
FCK[3:0]
0 0
Value after reset:
b15 b14
— —
0 0
Value after reset:
Bit Symbol Bit Name
b3 to b0 PCKD[3:0]
Peripheral Module Clock D
(PCLKD) Select
b7 to b4 —
Reserved
b11 to b8 PCKB[3:0] Peripheral Module Clock B
(PCLKB) Select
b19 to b12 — Reserved
b23 to b20 — Reserved
b27 to b24 ICK[3:0] System Clock (ICLK)
Select
b31 to b28 FCK[3:0] FlashIF Clock (FCLK)
Select
Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
This register cannot be rewritten while the flash memory is being programmed or erased.
When an instruction for writing to SCKCR or SCKCR3 is to follow writing to the SCKCR register, do so in accord with
the procedure below.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b29 b28 b27 b26
ICK[3:0]
1 1 0 0
b13 b12 b11 b10
— — PCKB[3:0]
0 0 0 0
Description
b3
0 0 0 0: ×1
0 0 0 1: ×1/2
0 0 1 0: ×1/4
0 0 1 1: ×1/8
0 1 0 0: ×1/16
0 1 0 1: ×1/32
0 1 1 0: ×1/64
Settings other than above are prohibited.
These bits are read as 0. The write value should be 0.
b11
0 0 0 0: ×1
0 0 0 1: ×1/2
0 0 1 0: ×1/4
0 0 1 1: ×1/8
0 1 0 0: ×1/16
0 1 0 1: ×1/32
0 1 1 0: ×1/64
Settings other than above are prohibited.
These bits are read as 0. The write value should be 0.
These bits are read as 0. The write value should be 0.
b27
0 0 0 0: ×1
0 0 0 1: ×1/2
0 0 1 0: ×1/4
0 0 1 1: ×1/8
0 1 0 0: ×1/16
0 1 0 1: ×1/32
0 1 1 0: ×1/64
Settings other than above are prohibited.
b31
0 0 0 0: ×1
0 0 0 1: ×1/2
0 0 1 0: ×1/4
0 0 1 1: ×1/8
0 1 0 0: ×1/16
0 1 0 1: ×1/32
0 1 1 0: ×1/64
Settings other than above are prohibited.
b25 b24 b23 b22
— —
1 1 0 0
b9 b8 b7 b6
— —
1 1 0 0
b0
b8
b24
b28
9. Clock Generation Circuit
b21 b20 b19 b18
— — — —
0 0 0 0
b5 b4 b3 b2
— — PCKD[3:0]
0 0 0 0
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b17 b16
— —
0 0
b1 b0
1 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W