Control Register 3 (Cr3); Port Control Register (Pcr) - Renesas RX100 Series User Manual

RX13T Group
23.2.24

Control Register 3 (CR3)

Address(es): SCI12.CR3 0008 B324h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 SDST Start Frame Detection Start
b7 to b1 — Reserved
SDST Bit (Start Frame Detection Start)
Detection of a Start Frame begins when this bit is set to 1. The bit is read as 0.
23.2.25

Port Control Register (PCR)

Address(es): SCI12.PCR 0008 B325h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 TXDXPS TXDX12 Signal Polarity Select
b1 RXDXPS RXDX12 Signal Polarity
Select
b3, b2 — Reserved
b4 SHARPS TXDX12/RXDX12 Pin
Multiplexing Select
b7 to b5 — Reserved
SHARPS Bit (TXDX12/RXDX12 Pin Multiplexing Select)
When this bit is set to 1, the TXDX12 and RXDX12 signals are multiplexed on the same pin so that half-duplex
communications become possible.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — — —
0 0 0 0
Description
0: Detection of Start Frame is not performed.
1: Detection of Start Frame is performed.
These bits are read as 0. The write value should be 0.
b5 b4 b3 b2
SHARP RXDXP
— — —
S
0 0 0 0
Description
0: The polarity of TXDX12 signal is not inverted for output.
1: The polarity of TXDX12 signal is inverted for output.
0: The polarity of RXDX12 signal is not inverted for input.
1: The polarity of RXDX12 signal is inverted for input.
These bits are read as 0. The write value should be 0.
0: The TXDX12 and RXDX12 pins are independent.
1: The TXDX12 and RXDX12 signals are multiplexed on the same
pin.
These bits are read as 0. The write value should be 0.
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
— SDST
0 0
b1 b0
TXDXP
S S
0 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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